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cornell-c2s2 / c2s2_ip

A general repository for all of C2S2's IP, including testing
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Generating SRAMs #31

Open gabizon103 opened 9 months ago

gabizon103 commented 9 months ago

We will probably want to have SRAMs in our design. Memories can be "modeled" in Verilog, but they will get synthesized to a bunch of registers instead of actual memories. Instead, we will need to use an SRAM generator. More details to follow.

Next steps: do more research, play around with OpenRAM

UnsignedByte commented 9 months ago

Extra context for this:

srams.v whichi s currently in cmn is non-synthesizable (and if synthesizable, has the problems outlined by ethan. Although the caravel harness already has ram built in, this would still be an interesting project to work on and might be helpful if we want to have memory access without having to use the wishbone bus.