[Schedule][Backend][SODA] Introduce stencil primitive

[seanlatias]

Main modification

In this PR, we introduce the stencil primitive. Following is an example,

def kernel(A):
    return hcl.compute((8, 8), lambda y, x: A[y][x] + A[y+2][x+2], "B")
A = hcl.placeholder((10, 10))
s = hcl.create_schedule(A, kernel)
s[kernel.B].stencil()
f = hcl.build(s, target='vhls')

With the above code, the backend code generator calls the SODA HLS codegen. This results in three files. The one returned by the build function, a header file contains the prototype of stencil call, and a cpp file contains the implementation of the stencil call. If multiple stencil primitives are used, only one header file will be generated while multiple cpp files are generated.

To apply to a multi-stage stencil, we need to explicitly wrap them in a stage. Following is an example,

def kernel(A):
    with hcl.Stage("S"):
        B = hcl.compute((8, 8), lambda y, x: A[y][x] + A[y+2][x+2], "B")
        C = hcl.compute((6, 6), lambda y, x: B[y][x] + B[y+2][x+2], "C")
A = hcl.placeholder((10, 10))
s = hcl.create_schedule(A, kernel)
s[kernel.S].stencil()
f = hcl.build(s, target='vhls')

Other changes

1. Rewrite the SODA code to make it consistent with other TVM passes 1.1. SODA code are now under tvm, ir namespace instead of HalideIR, Internal 1.2. Add "soda" namespace for later use if we have other stencil analyzers other then SODA 1.3. Move most of the function definitions from the header file to the source files 1.4. Reuse the code generation from SODA to code generation in VHLS
2. Introduce "Stencil" IR node 2.1. During storage flatten, collect the input/output tensor of the stencil region
3. Now the VHLS only prints types with ap_int, ap_uint instead of int/unsigned int

TODO

Now the HLS codegen for SODA does not work as desired.