[Roadmap] HeteroCL Release Note v0.3

[seanlatias]

Release Note

We are happy to announce that v0.3 is released. Since Python 2 is deprecated, we will be supporting Python 3 from now on.

General API

• hcl.print (#178)
• hcl.struct (#157)

For hcl.struct, we only support CPU simulation and Xilinx toolchain (e.g. Vivado HLS). The Intel toolchain support will be introduced in the next release.

Data Streaming

• hcl.to (#140, #167)

With this new feature, users can specify data placement and data movement in a decoupled way. Currently, CPU simulation is still under development. We will release it in the next version.

Back-end Support

• Code generation for both Intel and Xilinx platforms (#140, #162)
• Integration with HLS IPs (#170)

We implemented several code generation passes for common FPGA back ends for different toolchains, including Xilinx Vitis and Intel AOCL. We also integrate HLS IPs with HeteroCL. Users can now use existing HLS IPs. We are working on integrating with RTL IPs, which will be introduced in the next version.

Front-end Support

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• Integrate with Keras via Relay (#142)

We added a front-end pass that connects HeteroCL with Keras. We use Relay as a parser and graph builder. More front ends will be introduced in the later versions.

[chhzh123]

As we have released a new version of HeteroCL that entirely moves the compilation stack to MLIR, issues related to the original HalideIR flow will be closed.