[Backend] VHLS CodeGen SDSoC mode (legacy support)

[hecmay]

The main difference between SDSoC VHLS code and Vitis/SDAccel is the system memory allocation APIs (SDSoC uses sds_alloc and sds_free) and kernel function header pragmas.

1. Use sds_alloc for memory allocation on host program
2. Modified StreamExpr to contain index information (this can be also useful for the access pattern analysis in the next streaming enhancement PR)

Example of compiling with SDSoC in python

    target = hcl.platform.zc706
    s = hcl.create_schedule([A], kernel)
    s.to(kernel.B, target.xcel)
    s.to(kernel.C, target.host)
    target.config(compile="sdsoc", mode="sw_sim")
    f = hcl.build(s, target)

Example of generated host code:

  ap_int<32>* B_channel = sds_alloc(sizeof(ap_int<32>)*10*32);
  for (ap_int<32> B0 = 0; B0 < 10; ++B0) {
    for (ap_int<32> B1 = 0; B1 < 32; ++B1) {
      B_channel = B[(B1 + (B0 * 32))];
    }
  }
  ap_int<32>* C_channel = sds_alloc(sizeof(ap_int<32>)*10*32);
  test(B_channel, C_channel);