cornell-zhang / heterocl

HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing
https://cornell-zhang.github.io/heterocl/
Apache License 2.0
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SODA backend cannot generate XHLS code #213

Closed hecmay closed 4 years ago

hecmay commented 4 years ago

Minimal test case to reproduce error:

def test_stencil_multi_stencil():
    A = hcl.placeholder((10, 10), "A")
    def kernel(A):
        B = hcl.compute((10, 8), lambda y, x: A[y, x] + A[y, x+1] + A[y, x+2], "B")
        C = hcl.compute((8, 8), lambda y, x: B[y, x] + B[y+1, x] + B[y+2, x], "C")
    s = hcl.create_schedule(A, kernel)
    s[kernel.B].stencil(burst_width=256, unroll_factor=4)
    s[kernel.C].stencil(burst_width=128, unroll_factor=8)
    print(hcl.build(s, target='soda_xhls'))

The generated IR is correct, but SODAC failed to generate XHLS code from the IR

[21:54:06] src/codegen/build_soda.cc:90: ERROR:sodac:130: None:10:1: error: Expected '*' or '/' or '%' or '+' or '-' or '<=' or '>=' or '<' or '>' or '==' or '!=' or BinaryAndOp or XorOp or BinaryOrOp or LogicAndOp or LogicOrOp or 'local' or 'output' or 'param' at position (10, 1) => '(2, 0)))) *'.

@Blaok

Blaok commented 4 years ago

The SODA backend is not aware of the Stencil IR node. I'll work on it.

Blaok commented 4 years ago

Question about the semantics: the above example contains two separate Stencil IR nodes. What should I return from hcl.build? HLS code concatenated?

hecmay commented 4 years ago

I think so. It is supposed to return the concatenated HLSC kernel code, or use the similar semantics for Stencil Nodes in VHLS CodeGen (e.g. return the function calls only and save the definition inside a separate file)? @seanlatias What do you think?

hecmay commented 4 years ago

And also a follow-up to the issue. The program above cannot run through the Vivado HLS CodeGen (i.e. hcl.build(s, target="vhls")). The error message is as followed:

[21:16:58] src/codegen/build_soda.cc:90: Traceback (most recent call last):
  File "/work/shared/users/phd/sx233/heterocl/soda/src/sodac", line 139, in <module>
    main()
  File "/work/shared/users/phd/sx233/heterocl/soda/src/sodac", line 127, in main
    xocl.print_code(stencil, args)
  File "/work/shared/users/phd/sx233/heterocl/soda/src/soda/codegen/xilinx/opencl.py", line 36, in print_code
    kernel.print_code(stencil, tmp)
  File "/work/shared/users/phd/sx233/heterocl/soda/src/soda/codegen/xilinx/hls_kernel.py", line 173, in print_code
    burst_width=stencil.burst_width)
  File "/work/shared/users/phd/sx233/heterocl/soda/src/soda/codegen/xilinx/hls_kernel.py", line 282, in _print_module_definition
    raise util.InternalError('cannot process such a burst yet')
haoda.util.InternalError: cannot process such a burst yet

Another question about how we can connect those stencil kernels with FIFOs: each stencil node is mapped to a sub-kernel function with m_axi interfaces, and there are corresponding BurstRead and BurstWritefunctions inside to stream the data into/from the streaming channels. Can SODAC generate HLSC code fr Stencil node without the AXIS master interfaces, and replace it with the streaming channels?

Blaok commented 4 years ago

The error is supposed to go away with the Stencil IR node being used.

Regarding integration, replacing m_axi with a streaming interface is certainly doable.

  1. I'll add a new backend to SODA that generates HLS code with axis interface instead of m_axi.
  2. The axis interface will not support TLAST to remove some resource overhead. This requires that whoever reading from the interface must know when to stop by itself (which is likely the case because it knows the loop trip count).
  3. The HLS code is only supposed to be used for software simulation. For hardware simulation/bitstream generation, xo files must be exported directly from SODA to guarantee full pipelining.
  4. I'll update the SODA documentation with details about the data layout.

I probably won't have bandwidth to actually implement those until the ICCAD deadline. I'll keep you posted.

hecmay commented 4 years ago

Thanks! It's totally fine. No rush.

I will also update the IR integration part to support importing RTL modules. We can discuss later after the deadline.