ERROR: [v++ 203-801] Interface parameter bitwidth 'A.V' (heterocl-demo/s1-project/kernel.cpp:15:1)
must be a multiple of 8 for AXI4 master port.
ERROR: [v++ 200-70] Failed building synthesis data model.
ERROR: [v++ 60-300] Failed to build kernel(ip) test, see log for details:
heterocl-demo/s1-project/_x.hw.xilinx_u280_xdma_201920_1/kernel/test/vivado_hls.log
ERROR: [v++ 203-801] Bitwidth of (packed) data on axi master must be power of 2:
Found 'input_image.V' (packed) has a bitwidth of 160.
ERROR: [v++ 200-70] Failed building synthesis data model.
ERROR: [v++ 60-300] Failed to build kernel(ip) test, see log for details:
heterocl-demo/bnn/lab5775/project/_x.hw_emu.xilinx_u280_xdma_201920_1/kernel/test/vivado_hls.log
ERROR: [v++ 60-599] Kernel compilation failed to complete
ERROR: [v++ 60-592] Failed to finish compilation
Both of them need to pad the input data to meet the constraints given by Vitis.
The interface generated by
.to
cannot pass the Vitis synthesis. An example is shown below.Another test case here.
Both of them need to pad the input data to meet the constraints given by Vitis.