With Xilinx HLS, inner loops are automatically unrolled if outer loops are pipelined. In HeteroCL, we follow the same idea. In other words, we only specify pipelined loops without specifying the inner loops to be unrolled. However, this does not apply to Intel tools. Thus, we should automatically mark all inner loops to be unrolled if outer loops are pipelined.
With Xilinx HLS, inner loops are automatically unrolled if outer loops are pipelined. In HeteroCL, we follow the same idea. In other words, we only specify pipelined loops without specifying the inner loops to be unrolled. However, this does not apply to Intel tools. Thus, we should automatically mark all inner loops to be unrolled if outer loops are pipelined.