HCL runtime always uses the default config of the EDA tools for post implementation (e.g. target frequency, strategies for placement & routing, physical optimization, e.t.c). We need to add an interface to HCL to allow users to configure those options.
Here is some configurations I used in the auto-tuning tools for FPGA synthesis.
For most of the time, after randomly sampling the search space, we can get around 10% improvement on frequency. E.g. for the SuSy GEMM design, we can get a design point with F=210MHz compared with the default (F=193MHz).
The PR #321 will be separated into multiple smaller PRs. This feature will be introduced in one of them.
HCL runtime always uses the default config of the EDA tools for post implementation (e.g. target frequency, strategies for placement & routing, physical optimization, e.t.c). We need to add an interface to HCL to allow users to configure those options.
Here is some configurations I used in the auto-tuning tools for FPGA synthesis.
Intel AOCL options table
For most of the time, after randomly sampling the search space, we can get around 10% improvement on frequency. E.g. for the SuSy GEMM design, we can get a design point with F=210MHz compared with the default (F=193MHz).
The PR #321 will be separated into multiple smaller PRs. This feature will be introduced in one of them.