[API] Vitis support for report API

[yn224]

Add feature: This PR adds parsing support for reports produced by Vitis simulation.

How to use the new feature: The interface remains the same as Vivado case

f = top(p)
report = f.report()
report.display()

Detailed description: Similar parsing logic for Vivado report is used to parse the report data.

Link to the tests: tests/test_hls_report.py

[chhzh123]

Hi Alex @yn224 , thanks for contributing to HeteroCL! We're sorry to review your PR so late.

Could you give a simple example of your generated report here? It may be more intuitive to see whether your code needs to be further modified or not.

[yn224]

Hi Alex @yn224 , thanks for contributing to HeteroCL! We're sorry to review your PR so late.

Could you give a simple example of your generated report here? It may be more intuitive to see whether your code needs to be further modified or not.

Sure. Should I paste it in the comment section of report.py or somewhere else?

[chhzh123]

Hi Alex @yn224 , thanks for contributing to HeteroCL! We're sorry to review your PR so late. Could you give a simple example of your generated report here? It may be more intuitive to see whether your code needs to be further modified or not.

Sure. Should I paste it in the comment section of report.py or somewhere else?

You can just paste it into this PR discussion.

[yn224]

... You can just paste it into this PR discussion.

Some example outputs from the report API: sobel

+-------------------+-----------------------------------+
| HLS Version       | Vivado HLS 2019.1.3               |
| Product family    | zynq                              |
| Target device     | xc7z020-clg484-1                  |
| Top Model Name    | test                              |
+-------------------+-----------------------------------+
| Target CP         | 10.00 ns                          |
| Estimated CP      | 9.634 ns                          |
| Latency (cycles)  | Min 13724837; Max 13724837        |
| Interval (cycles) | Min 13724838; Max 13724838        |
| Resources         | Type        Used    Total    Util |
|                   | --------  ------  -------  ------ |
|                   | BRAM_18K    4108      280   1467% |
|                   | DSP48E        53      220     24% |
|                   | FF         11827   106400     11% |
|                   | LUT        20678    53200     39% |
|                   | URAM           0        0      0% |
+-------------------+-----------------------------------+

+-----------------------+--------------+-----------+---------------------+---------------+------------------+
|                       |   Trip Count |   Latency |   Iteration Latency |   Pipeline II |   Pipeline Depth |
|-----------------------+--------------+-----------+---------------------+---------------+------------------|
| P_x1                  |          412 |   8643760 |               20980 |           N/A |              N/A |
| + P_y                 |          617 |     20978 |                  34 |           N/A |              N/A |
| ++ P_z                |            3 |        15 |                   5 |           N/A |              N/A |
| A_x3                  |          412 |   4068088 |                9874 |           N/A |              N/A |
| + A_y1                |          617 |      9872 |                  16 |           N/A |              N/A |
| Y_x_reuse_Y_y_reuse   |       254204 |    254325 |                 N/A |             1 |              123 |
| X_x_reuse1_X_y_reuse1 |       254204 |    254325 |                 N/A |             1 |              123 |
| R_x6_R_y2             |       252150 |    252173 |                 N/A |             1 |               25 |
| F_x7_F_y3             |       252150 |    252156 |                 N/A |             1 |                8 |
+-----------------------+--------------+-----------+---------------------+---------------+------------------+
* Units in clock cycles

sobel_pipelined - pipeline attempt of sobel

+-------------------+-----------------------------------+
| HLS Version       | Vitis HLS 2019.1.3                |
| Product family    | virtexuplus                       |
| Target device     | xcu280-fsvh2892-2L-e              |
| Top Model Name    | test                              |
+-------------------+-----------------------------------+
| Target CP         | 3.33 ns                           |
| Estimated CP      | 2.633 ns                          |
| Latency (cycles)  | Min 2207343; Max 2207343          |
| Interval (cycles) | Min 2207344; Max 2207344          |
| Resources         | Type        Used    Total    Util |
|                   | --------  ------  -------  ------ |
|                   | BRAM_18K      98     4032      2% |
|                   | DSP           51     9024      1% |
|                   | FF         22099  2607360      1% |
|                   | LUT        26916  1303680      2% |
|                   | URAM           0      960      0% |
+-------------------+-----------------------------------+

+-----------------------+--------------+-----------+-------------------------+---------------+------------------+
|                       |   Trip Count |   Latency |   Absolute Time Latency |   Pipeline II |   Pipeline Depth |
|-----------------------+--------------+-----------+-------------------------+---------------+------------------|
| B_x_B_y               |       368200 |   1104614 |                 3681678 |             3 |               18 |
| E_x_reuse_E_y_reuse   |       368200 |    368330 |                 1227643 |             1 |              132 |
| D_x_reuse1_D_y_reuse1 |       368200 |    368330 |                 1227643 |             1 |              132 |
| Fimg_x3_Fimg_y1       |       365752 |    365784 |                 1219158 |             1 |               34 |
+-----------------------+--------------+-----------+-------------------------+---------------+------------------+
* Units in clock cycles

digitrec found under samples directory

+-------------------+-----------------------------------+
| HLS Version       | Vitis HLS 2019.1.3                |
| Product family    | virtexuplus                       |
| Target device     | xcu280-fsvh2892-2L-e              |
| Top Model Name    | test                              |
+-------------------+-----------------------------------+
| Target CP         | 3.33 ns                           |
| Estimated CP      | 2.744 ns                          |
| Latency (cycles)  | Min 20080 ; Max 20080             |
| Interval (cycles) | Min 20081 ; Max 20081             |
| Resources         | Type        Used    Total    Util |
|                   | --------  ------  -------  ------ |
|                   | BRAM_18K      32     4032      1% |
|                   | DSP            0     9024      0% |
|                   | FF          7559  2607360      0% |
|                   | LUT        34172  1303680      3% |
|                   | URAM           0      960      0% |
+-------------------+-----------------------------------+

+---------------------------------------------+--------------+-----------+-------------------------+---------------+------------------+
|                                             |   Trip Count |   Latency |   Absolute Time Latency |   Pipeline II |   Pipeline Depth |
|---------------------------------------------+--------------+-----------+-------------------------+---------------+------------------|
| train_images_burst_r0_train_images_burst_r1 |        18000 |     18002 |                   60000 |             1 |                4 |
| knn_mat_burst_r0_knn_mat_burst_r1           |           30 |        30 |                      99 |             1 |                2 |
| knn_update_y1                               |         1800 |      1803 |                    6009 |             1 |                5 |
| knn_mat_burst_s0_knn_mat_burst_s1           |           30 |        31 |                     103 |             1 |                3 |
+---------------------------------------------+--------------+-----------+-------------------------+---------------+------------------+
* Units in clock cycles

[chhzh123]

The reports look great! Thanks for posting them. It would be even better if you can add a latency summary (clock cycles & estimated time) of the whole design, which can also be retrieved from the HLS report.

[yn224]

The reports look great! Thanks for posting them. It would be even better if you can add a latency summary (clock cycles & estimated time) of the whole design, which can also be retrieved from the HLS report.

Those were already being supported but I just updated the comment above with estimated times. I had to fix some code to display properly.

[chhzh123]

The reports look great! Thanks for posting them. It would be even better if you can add a latency summary (clock cycles & estimated time) of the whole design, which can also be retrieved from the HLS report.

Those were already being supported but I just updated the comment above with estimated times. I had to fix some code to display properly.

Cool! Please let me know if you have already fixed other issues.

[yn224]

The reports look great! Thanks for posting them. It would be even better if you can add a latency summary (clock cycles & estimated time) of the whole design, which can also be retrieved from the HLS report.

Those were already being supported but I just updated the comment above with estimated times. I had to fix some code to display properly.

Cool! Please let me know if you have already fixed other issues.

I think it is ready for a review again. I think I have committed all the edits I think was necessary.

[chhzh123]

I've run your PR and reviewed it again. There're some minor changes above. Can you also add imageio into python/setup.py? Since your sobel example uses that library.

[yn224]

@chhzh123 I think it is ready for a review again.

[hecmay]

@chhzh123 Thank you. LGTM. I will merge it now.