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cpc / openasip

Open Application-Specific Instruction Set processor tools (OpenASIP)
http://openasip.org
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FUGen should not require verilog #174

Closed pjaaskel closed 2 years ago

pjaaskel commented 2 years ago

In the RISC-V tutorial we now need to add a dummy Verilog file although we do not want to generate Verilog, which seems unoptimal.