The manual asks to set this to 5. However, for me this creates a mismatch in bustrace diffs between ttasim and ghdl-simulation.
Setting bustracestartingcycle to 6 seems to work.
Has there been some change in the ICDecoder or something that adds one more cycle of latency to the generated RTL?
The manual asks to set this to 5. However, for me this creates a mismatch in bustrace diffs between ttasim and ghdl-simulation. Setting bustracestartingcycle to 6 seems to work.
Has there been some change in the ICDecoder or something that adds one more cycle of latency to the generated RTL?