Cleanup testbench code

[nrother]

The current testbench code generated by testhdb had some problems for me, GHDL would exit with error: overflow. I took this as an opportunity to clean up the testbench a little bit.

Since GHDL supports VHDL-2008 since version 0.33 and Ubuntu ships 0.37 or newer I made use of the to_hstring() function of VHDL-2008. This remove a lot of code from the testbench. Also I removed the deprecated Std_Logic_arith package.

The output now contains hex strings for actual and expected, which might or might not be desired:

tb_fu_1.vhdl: TCE Assert: Verification failed at cycle 1 output: 5883B403 expected: EE2E0160

The generated code looks like this

if current_cycle >= IGNORE_OUTPUT_COUNT then
 assert data_out1_out = data_out1_out_data(current_cycle)
    report lf & "TCE Assert: Verification failed at cycle " & integer'image(current_cycle)
    & " output: " & to_hstring(data_out1_out)
    & " expected: " & to_hstring(data_out1_out_data(current_cycle))  severity error;

end if;

Someone should test this with the Modelsim backend.

[pjaaskel]

Looks useful. Can you test with modelsim @karihepola ?

[karihepola]

I tested out the PR. The test suite passes and testhdb works with the ModelSim simulator.