RISC-V long systemtest fail if RISC-V support is not enabled

[pjaaskel]

FAIL: ./procgen/RISCV/tcetest_bypass.sh: Generate RISCV processor with bypasses and simulate [nonzero (2) exit code]
./tcetest_bypass.sh: line 14: eexit: command not found
FAILURE: RTL itrace does not exist
FAIL: ./procgen/RISCV/tcetest_stdlib.sh: Test stdlib with RISCV [nonzero (1) exit code]
cp: cannot stat 'proge-output/tb/imem_init.img': No such file or directory
FAIL: ./procgen/FUGen/tcetest_fugen.sh: Compares FUGen-generated RTL and ttasim bustrace [nonzero (1) exit code]
GHDL not found in path.
The target architecture has bothconditional moves and select instruction.Ignoring select and using conditional moves instead
FAIL: ./procgen/RISCV/tcetest_no_bypass.sh: Generate RISCV processor without bypasses and simulate [nonzero (2) exit code]
./tcetest_no_bypass.sh: line 14: eexit: command not found
FAILURE: RTL itrace does not exist

It should disable the tests that are not expected to pass.