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cpc / openasip

Open Application-Specific Instruction Set processor tools (OpenASIP)
http://openasip.org
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custom generator script called from ProGen #7

Closed boehmerst closed 8 years ago

boehmerst commented 8 years ago

Hello all,

I would like to use TCE within a Verilog flow. To keep as flexible as possible I currently design FUs in a generator language called Chisel that is able to compile into Verilog, C++ and VHDL code. Unfortunately any generics and parameters (e.g. for RF size, data widths or latencies) are resolved during code generation resulting in generator reruns and regular HDB updates. Is it possible to define custom callback scripts referenced in HDB (instead of the actual HDL files) being called and configured with FU parameters during processor generation? Actually, very much in the sense of code generators in IP-XACT?

Regards, Stephan

pjaaskel commented 8 years ago

HDBs are Sqlite databases, could you create a script that modifies the entries via SQL? P.S. the mailing lists are meant for questions like this.thx.