Consider re-submitting your design to GF-MPW-0

[proppy]

GF-MPW-0

We recently announced a new OpenMPW shuttle run for the GF180MCU PDK. Would you consider resubmitting your design to https://platform.efabless.com/shuttles/GFMPW-0?

Jacaranda-8 with GF180MCU

I tried to re-harden your project macro successfully in this colab notebook: https://colab.research.google.com/gist/proppy/7bf5a57f6e9b39889b44ef7388897063/jacaranda-8-openlane-gf180mcu.ipynb with the following config.json configuration:

{
    "DESIGN_NAME": "computer",
    "DESIGN_IS_CORE": 0,
    "VERILOG_FILES": [
      "defines.v",
      "dir::jacaranda-8/*.v",
      "dir::jacaranda-8/UART/*.v"
    ],
    "CLOCK_PERIOD": 500,
    "CLOCK_PORT": "wb_clk_i",
    "CLOCK_NET": "wb_clk_i",
    "FP_SIZING": "absolute",
    "DIE_AREA": "0 0 2000 2000",
    "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
    "PL_BASIC_PLACEMENT": 0,
    "PL_TARGET_DENSITY":  0.40,
    "VDD_NETS": ["vccd1"],
    "GND_NETS": ["vssd1"],
    "DIODE_INSERTION_STRATEGY": 4,
    "pdk::gf180mcuC": {
        "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
        "RT_MAX_LAYER": "Metal4",
        "SYNTH_MAX_FANOUT": 4
    }
}

See the layout below: computer.gds.zip

Steps

• [ ] Go to https://github.com/efabless/caravel_user_project/generate to create a new project or copy the updated files to this repo.
• [ ] Run the following commands to configure GF180MCU PDK:

  export PDK=gf180mcuC
  make setup

• [ ] Integrate the RTL from verilog/rtl/jacaranda-8/ in the project.
• [ ] Integrate the new config.json configuration (make sure to update the VERILOG_FILES appropriatly.
• [ ] Re-harden your macro and the wrapper:

  make computer
  make user_project_wrapper

  (see https://caravel-user-project.readthedocs.io/en/latest/index.html#starting-your-project for more details)

• [ ] Submit the project to https://platform.efabless.com/shuttles/GFMPW-0

[proppy]

Done! https://platform.efabless.com/projects/1651