search

cpuex2019-yokyo / core

RISC-V (rv32imf) CPU implemented in System Verilog for cpuex2019 @ UTokyo
13 stars 0 forks source link

Add interface(s) for M-mode interrupts to PLIC #25

Closed lmt-swallow closed 4 years ago

lmt-swallow commented 4 years ago

It should be implemented as described in priv v1.10.0. I

That specification seems to have no mentions on the difference of M-mode interrupts and S-mode ones, but I believe you CAN do, @TakutoMitsunobu :-)