Closed mdko closed 4 years ago
Looks like this is due to comments from Yosys about the relevant source code line that are dumped in the btor2 now. This PR should fix it https://github.com/cristian-mattarei/CoSA/pull/129. It should be merged soon.
Also, depending on your use-case, you might consider looking at: https://github.com/upscale-project/pono. It uses the official BTOR2 parser so should be more robust to these kinds of issues.
When I run
CoSA --problems examples/counters/problem_verilog.txt
from within my unmodifiedCosA
repo copy, it complains that it cannot access the symbolcounter_2.out
when trying the task[counter_2_reaches_1]
:Do I need to add an output to the top-level Verilog module for each signal I wish to check, or is accessing the internal wires of Verilog modules supported like in CoreIR
.json
files?Thanks!