Internal signals don't work after Verilator update

csail-csg / pyverilator

Python wrapper for verilator model

MIT License

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Internal signals don't work after Verilator update #8

Open acw1251 opened 4 years ago

acw1251 commented 4 years ago

pyverilator finds internal signals by parsing VL_SIG* lines in an .h file generated by verilator. The most recent version of verilator looks like it doesn't use the VL_SIG* macros anymore. Instead it, for an 8-bit signal, it produces a line like the one below:

CData/*7:0*/ parent_module__DOT__in_reg;

pyverilator should also look for this format as well.

acw1251 commented 4 years ago

It looks like this is the Verilator commit that introduced this bug: https://github.com/verilator/verilator/commit/21a380def0803789a92e00aa3f37a43fd4d804a2 Until pyverilator is updated to support this new format, you can revert to Verilator v4.020 or earlier to get rid of this problem.