Verilog is not properly highlighted while encounter single quote mark .

[GoogleCodeExporter]

When encounter "'" , for example "1'b1" in verilog , the color generator will 
misunderstood the " '  " mark as an special character for quoting the string, 
and consequently highlight the text between each " ' " mark.

sorry for reporting here, it'll be a lot help for me if this problem can be 
fixed.

THX!!

Original issue reported on code.google.com by jeffrey8...@gmail.com on 17 Nov 2014 at 4:40

Attachments:

• screenshot.png