Research FPGA-optimized networks and pick architecture

[kodachi77]

Review major architectures and techniques that are hardware friendly:

• quantization
• binarization (full and partial)
• XNOR networks

DOD

• [x] chose network to implement on Zybo-Z7-20

[kodachi77]

For more details see:

• FPGA-Based BNN Architecture in Time Domain with Low Storage and Power Consumption
• FINN: A Framework for Fast, Scalable Binarized Neural Network Inference

[kodachi77]

Considering constraints of the platform coupled with the fact that "full" platform consumes 40% of available FPGA resources we will use SFC architecture described in FINN paper. It is effectively 3 FC layers fully binarized with 256 neurons each.

Current goal is to achieve at least 93-95% accuracy.

We will start from 1bit activation and 1bit weights. Then increase if we fail accuracy threshold.