Closed cube1us closed 3 years ago
If a switch occupies two logic blocks (example, page 40.10.01.1) when they are merged, the HDL is generated properly, but the test bench ends up with duplicate signals and port map entries.
Fixed
If a switch occupies two logic blocks (example, page 40.10.01.1) when they are merged, the HDL is generated properly, but the test bench ends up with duplicate signals and port map entries.