Open calebmkim opened 1 year ago
(Mainly writing this down for my future reference so I don't forget it).
Having the following component signatures:
systolic_array(...)(... r1_valid, r1_value, r1_idx, r2_valid, r2_value, r2_idx, etc.)
post_op(r1_valid, r1_value, r1_idx, r2_valid, r2_value, r2_idx, etc.)
And the following group to control the coordination (the actual group may look slightly different):
// group will be very ugly looking
group perform_op {
// something
systolic_array.go = !systolic.array.done ? 1'd1;
// other systolic array input ports
post_op.r1_valid = systolic_array.r1_valid;
post_op.r1_value = systolic_array.r1_value;
// etc.
perform_op[done] = post_op.done
}
We should not do the following:
par {invoke systolic_array; invoke post_op;}
since there is no guarantee about the relative ordering of threads of par
blocks.
(These ideas are not necessarily mutually exclusive, just a list of things we could discuss)
Ideas
A.tile(i, ii, II)
andA.unroll(i, …)
commands into Calyx designs)? Or do we want to try to look at what their case studies are doing and see if we can generate a Calyx design that generates the same thing?Implementation Details