Trying to get Hector to work

[calebmkim]

Before getting the Hector systolic array stuff to work we have to get a) Hector working and b) hector_template (which has a bunch of chisel templates) working.

I have cloned Hector /scratch/cmk265/learning/Hector and hector_template into /scratch/cmk265/learning/hector_template (on Havarti). I seem to remember having Hector working over the summer but sadly now nothing is working for some reason.

Hector Not Working

Hector is not working. I have cloned the LLVM version into /scratch/cmk265/learning/llvm-hectorv and have checked out the appropriate branch. Yet it gives me this error: error.txt.

hector_template not working

hector_template is not working either. I need to install mill, but mill complains when it sees the repo's build instructions. This is the error it gives me: error.txt. If I use some generic build instructions, e.g., the simple build.sc on mill's website then it compiles correctly.

Calyx To-Dos

Things I can do in addition to trying to get Hector to work

• Fud Floating Point Support?
• Fully Static Implementation (no dynamic contraction dimension)

[calebmkim]

So Hector works if I point it towards the LLVM subdirectory inside of CIRCT (obviously I have to check out the right LLVM branch to make it work). But if I just clone LLVM regularly (and check out the right branch) Hector errors. Weird.

This is probably why it worked for me this past summer: I was trying to be quick so I just checked out and built the LLVM subdirectory that I was working w/ in CIRCT and it worked.

[sampsyo]

Weird indeed. I guess it's a matter of one of these extremely specific dependencies on a particular LLVM commit?

[calebmkim]

Update: so I actually think I got some of the Hector Systolic Array stuff (mostly) working. You can see the generated Verilog code here.

Couple of observations:

1) For synthesis, they use an IP Generator for the floating point multiplication/addition. (I had to play around with their code a tiny bit, but I got it to generate the synthesis stuff correctly (or at least it looks correct). This is the part I don't think is working: the tcl file they generate doesn't generate any IP commands (i.e., there are no commands to generate the black-box verilog code) and it still has aeloss_push as the design name. I noticed that their IPLogger.scala file, which is supposed to be generating these IP commands has a "TODO: FixMe" comment. I could email them to ask about the synthesis of thier Systolic Array maybe?

2) They also have delay units which are basically Chisel primitives that they can use to stall the PEs in the systolic array. This will probably make it an unfair resource comparison if we choose to compare, since they'll have extra stalling logic that we don't have.

[calebmkim]

Closing because they Hector uses weight stationary design compared to our output stationary design.