Designs to Implement

[rachitnigam]

Here is an ever-growing collection of designs to implement in Filament as well as interesting links worth reading.

FFT

• FFT Generator
• FFT + CORDIC
• Chisel FFT

Papers

• Parametric implementation of benchmarks from Aetherling paper
• Genome Kernel
• Crypto/ECC/Homomorphic accelerators
• Systolic arrays
• Hardware debugging paper from Michigan people
• FINN matrix-vector RTL

Processors

• RISC-V, especially if we show going from 3-stage to 5-stage pipeline we get the right errors
  • PicoRV32 from Chris batten’s class

Actionable Apps

• Applications from: https://github.com/KastnerRG/pp4fpgas
• CORDIC: https://github.com/cebarnes/cordic/blob/master/cordic.v
• Multiply core generator: https://github.com/ZipCPU/fwmpy
• FloPoCo: http://www.flopoco.org/
• DSP filters: https://github.com/ZipCPU/dspfilters
• Polynomial multipliers: https://arxiv.org/pdf/2110.12127.pdf
• Accelerators: https://github.com/aolofsson/awesome-opensource-hardware#accelerators
• HardCaml libs: https://blog.janestreet.com/growing-the-hardcaml-toolset-index/
• Spiral hardware generators
• Efficient Multi-Cycle Folded Integer Multipliers
• zk-SNARK accelerator from Jane Street

Less Actionable

• Match action tables?
  • Memories have a specific latency
  • Some network processing function
  • They are often fixed-latency
• Extract pipelines from Rosetta benchmarks
  • Rosetta: https://github.com/cornell-zhang/rosetta
• Polybench Benchmark Suite
• Kernels from google/xls?
• BF16 float mult

Links

• Pipelining: https://davidthings.github.io/spokefpga/pipelines

[rachitnigam]

Crossbar networks: "Typically there is trade off between the size of hardware resources (gates, flip flops, wires) and measures of congestion, such as bisection bandwidth"

[rachitnigam]

FIR Filter with Vivado synthesis analysis

[rachitnigam]

Educational RISC-V implementation: https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/README.md

CC @gabizon103

[rachitnigam]

The Genesis 2 project from Stanford has a bunch of publications on generators they built: https://github.com/StanfordVLSI/Genesis2/wiki/Publications

[rachitnigam]

vlsiffra parameterized adders and multipliers implemented using Amaranth HDL

[rachitnigam]

Vitis BLAS library: https://xilinx.github.io/Vitis_Libraries/blas/2022.1/index.html

Probably provides a reasonable baseline for an FPGA based BLAS implementation

[rachitnigam]

Constant-time curve25519