Open rachitnigam opened 1 year ago
Crossbar networks: "Typically there is trade off between the size of hardware resources (gates, flip flops, wires) and measures of congestion, such as bisection bandwidth"
Educational RISC-V implementation: https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/README.md
CC @gabizon103
The Genesis 2 project from Stanford has a bunch of publications on generators they built: https://github.com/StanfordVLSI/Genesis2/wiki/Publications
vlsiffra
parameterized adders and multipliers implemented using Amaranth HDL
Vitis BLAS library: https://xilinx.github.io/Vitis_Libraries/blas/2022.1/index.html
Probably provides a reasonable baseline for an FPGA based BLAS implementation
Here is an ever-growing collection of designs to implement in Filament as well as interesting links worth reading.
FFT
Papers
Processors
Actionable Apps
Less Actionable
Links