Geethanand Nagaraj - Githubissues

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Personal Details

Name: Geethanand Nagaraj

Major: M.Eng ECE

Year in Cornell & Expected graduation date: graduation expected on Dec-23

Relevant classes: ECE 5740, ECE 5775

Interested in continuing research during the summer? no

Expertise (languages/frameworks/etc.): Formal verification of RTL blocks written in verilog/SystemVerilog using Cadence JasperGold using system verilog assertions.
Functional verification of RTL blocks written in verilog/ SystemVerilog using Synopsys vcs. RTL design of certain specification or bus functional model for an interface to drive transactions into your RTL design in SV for verification using just SystemVerilog.

Research

When do you want to do research? This fall as a final semester M.Eng Design project for 3 credits as advised by M.Eng advisor Scott E. Coldren as this is a new project as I would not be continuing with Prof. Batten as he is going on a sabbatical and I was on leave of absence during spring but I would be grateful if this can be given for 4 credits for M.Eng design project as I will not have to take extra class to meet my M.Eng degree requirements credits where I fall short of 1 credit more. So I am also open for 1/2 credits of independent research if credits granted is 3/4 for M.Eng design project respectively so a total of 5 credits to complete my M.Eng would be helpful. (Researchers can get involved during the semester as an "extracurricular", equivalent to a 3-4 credit class, or get more involved over the summer as a full-time job.)

What is exciting to you about research? I am interested in computer architecture I am willing to contribute to any RTL IP being/developed in verilog/Sytemverilog that needs to be exhaustively verified through formal verification. Or if there is any block being/needs to be developed using systemverilog HDL which needs 100% bug free design I can collaborate with design and verification. If it is a subsystem or SoC then I have expertise in systemverilog-UVM using industry standard tools like synopsys vcs to conduct functional verification. (How did you get interested in it? What are you hoping to get out it?)

What kind of research do you want to do? primarily formal verification on smaller designs and functional verification using SV-UVM on larger designs. I am open to develop functional blocks using SystemVerilog HDL. (It's OK to say, "I don't know; I'm looking to explore!")

Background

Note: While these questions are optional for first & second year students, we highly encourage everyone to respond to them. Third & fourth year students are required to respond to all questions.

Was there a paper that particularly excited you? “Art of formal verification” by Prakash Math from Apple. (This doesn't have to be a paper from our group.)

Which of the current research projects would you be interested in working on and why? I am open to any project which has IP/blocks that you have developed or needs development where I can contribute by bug free designing through SystemVerilog or Verification through formal using cadence JG apps/functional using synopsys vcs through SV-UVM.

Anything else you want to tell us about yourself? Looking to complete my masters this December-23 and head back to industry.

Attach a CV/Resumé

GEETHANAND NAGARAJ 210 Lake Street, Auden Apartment 10C2, Ithaca, NY · +16073199212 gn223@cornell.edu · https://www.linkedin.com/in/geethanand-n-70a339266/ · geethanandnagaraj.com EXPERIENCE AUG-2015 – AUG-2022 SOC DESIGN ENGINEER/SR.PRE-SILICON VALIDATION ENGINEER/PRE-SILICON VALIDATION ENGINEER/GRADUATE TECHNICAL INTERN, INTEL, BANGALORE Worked on projects that taped out Intel’s first Omni-Path Architecture (OPA) and Intel’s first Infrastructure processing Unit (IPU) and later generations of products right from being an Intern to a Peripheral-subsystem lead: Responsible for integration of VIPs and verification closure. SOC verification of above mentioned SoC projects - Error/Interrupts/DMA flows testing. CPU (ARM based) subsystem verification - Functional RAL and Formal config register testing of 39 IPs – bring-up, touch test w/ attribute testing and test porting from Subsystem to SoC. Memory LP/DDR4 subsystem verification – VIP integration and end-to-end UVM scoreboard development w/ functional coverage and security, connectivity and register formal verification. Formal verification and functional verification various critical IPs – UVM & formal (bug hunting mode) verification from test planning to coverage closure. UVM bring up from scratch all TB/Test components w/ end to end IP level scoreboard development. TB and test porting from IP to subsystem level. EDUCATION DEC 2023 MASTERS IN ENGINEERING, CORNELL UNIVERSITY, ITHACA, NY Specialization in computer architecture and formal methods w/ Prof. Christopher Batten at CSL. JULY 2016 MASTERS IN TECHNOLOGY, RAMAIAH INSTITUTE OF TECHNOLOGY, BANGALORE Specialization in VLSI design and formal verification w/ Intel. JULY 2014 BACHELORS IN ENGINEERING, VISVESVARAYA TECHNOLOGICAL UNIVERSITY, BLR Specialization in RTL design from IISc, Bangalore w/ Dr. Santanu Mahapatra. SKILLS  Synopsys/Cadence VIP/verification tools  IP/Subsystem/SoC level verification  IAA-Intel Achievement Award winning team  UVM/Functional verification  Formal verification  System-Verilog/Assertions

cucapra / undergrad-research

Geethanand Nagaraj #108

Personal Details

Research

Background