AMD P-States Numbering

[cyring]

• Previous AMD processor families specifications

Software P-state Numbering

When referring to software P-state numbering, the following naming convention is used: • Non-boosted P-states are referred to as P0, P1, etc. • P0 is the highest power, highest performance, non-boosted P-state. • Each ascending P-state number represents a lower-power, lower performance non-boosted P-state than the prior P-state number. • Boosted P-states are referred to as Pb0, Pb1, etc. • Pb0 is the highest-performance, highest-power boosted P-state. • Each higher numbered boosted P-state represents a lower-power, lower-performance boosted P-state.

For example, if D18F4x15C[NumBoostStates] contains the values shown below, then the P-states would be named as follows:

D18F4x15C[NumBoostStates]=1	D18F4x15C[NumBoostStates]=3

P-state Name	MSR Address	P-state Name	MSR Address
Pb0	MSRC001_0064	Pb0	MSRC001_0064
P0	MSRC001_0065	Pb1	MSRC001_0065
P1	MSRC001_0066	Pb2	MSRC001_0066
P2	MSRC001_0067	P0	MSRC001_0067
P3	MSRC001_0068	P1	MSRC001_0068
P4	MSRC001_0069	P2	MSRC001_0069
P5	MSRC001_006A	P3	MSRC001_006A
P6	MSRC001_006B	P4	MSRC001_006B

• where:

D18F4x15C is the Core Performance Boost Control Register

Bits	Description
31:30	Reserved.
29	BoostEnAllCores: boost enable all cores. Read-write.
28:5	Reserved.
4:2	NumBoostStates: number of boosted states. Read-write. (CPB)
1:0	BoostSrc: boost source. Read-write.

What we learnt from CoreFreq

• Through function Compute_AMD_Zen_Boost : https://github.com/cyring/CoreFreq/blob/f6ba67a06676e3f83dfc4eeefb8b09683c39fc87/corefreqk.c#L3679

|- Frequency            (MHz)                      Ratio                        
                 Min    400.00                    <   4 >                       
                 Max   3600.00                    <  36 >                       
|- Factory                                                             [100.000]
                       3600                       [  36 ]                       
|- Performance                                                                  
   |- OSPM                                                                      
                 TGT   2200.00                    <  22 >                       
|- Turbo Boost                                                         [ UNLOCK]
                 XFR   4300.00                    [  43 ]                       
                 CPB   4200.00                    [  42 ]                       
                  1C   2800.00                    <  28 >                       
                  2C   2200.00                    <  22 >                       

• Decomposed:

Ratio	Variable	MSR Address	PstateEn	P-state Name
36	BOOST(MAX)	0xc0010064	Enable	Pb0
28	BOOST(1C)	0xc0010065	Enable	P0
22	BOOST(2C)	0xc0010066	Enable	P1
--	BOOST(3C)	0xc0010067	Disable	P2
--	BOOST(4C)	0xc0010068	Disable	P3
--	BOOST(5C)	0xc0010069	Disable	P4
--	BOOST(6C)	0xc001006a	Disable	P5
--	BOOST(7C)	0xc001006b	Disable	P6

• Whilst: CPB = 42 and XFR = 43 are computed ratios (based on the 3600X commercial datasheets)

https://github.com/cyring/CoreFreq/blob/f6ba67a06676e3f83dfc4eeefb8b09683c39fc87/corefreqk.h#L2952

• If we manage to write in [NumBoostStates] the value 3 @ PCI register address D18F4x15C we could re-run the function Compute_AMD_Zen_Boost and query the remaining Performance Boost P-States, in particular: Pb1 @ MSR 0xc0010065 and Pb2 @ MSR 0xc0010066

  I mean that rather than computing CPB (+6) and XFR (+1) from Pb0 (36), we could directly query their exact values from the hardware, respectively Pb1 and Pb2

• First let's see if we can dump this Core Performance Boost Control Register ?

EDIT: Instructions

## step 1: D18F4x15C is device 0x18 , function 4, register offset 0x15c
setpci -s 0x18.4 0x15c.L

## step 2: let's presumed a returned value of 0x20000000

## step 3: computes the hexadecimal of 0x20000000 OR 0x0c (to set value 3 in NumBoostStates)

## step 4: write the result 0x2000000c
setpci -s 0x18.4 0x15c.L=0x2000000c

## step 5: check the register is correctly written and returns 0x2000000c
setpci -s 0x18.4 0x15c.L

##  step 6: now read the PBO MSRs
rdmsr -aX 0xc0010065
rdmsr -aX 0xc0010066

## step 7: restore NumBoostStates to its original value (from step 2)
setpci -s 0x18.4 0x15c.L=0x20000000

## step 8: eventually, read the MSR again which should return different values
## (because we switch back to the non boosted p-states)
rdmsr -aX 0xc0010065
rdmsr -aX 0xc0010066

If one of those instructions failed, try to read the whole space

lspci -xxxx -s 0x18.4

Originally posted by @cyring in https://github.com/cyring/CoreFreq/issues/172#issuecomment-617705564

[cyring]

Going further into the subject; testing with Ryzen 3950X and the following boot options:

modprobe.blacklist=pcspkr,nouveau,k10temp,acpi_cpufreq idle=halt

• The OSPM Target plan shows that Cores remain in PB0 with a FID of 36

Driver development will add PB0 to the enumeration of ratios and see what I can do with it ...

[cyring]

• Apply 22 to all Cores

• Change Core #1 to 28

• Stress Core #0 which results to a ratio of 20 but we also see a ratio of 24 for Core #1

• FID of values { 20 , 24 } are not enumerated among the enabled P-States in function Compute_AMD_Zen_Boost() https://github.com/cyring/CoreFreq/blob/d38ca25c61ecfb2f46d6ff86cd40db7cb72e5077/corefreqk.c#L4470

P-State	FID	P-State	FID
P0	35	Pb0	36
P1	28	Pb1	24
P2	22	Pb2	20