Memory Controller of Tiger Lake/U

[cyring]

• Testing the MCHBAR

  
  PCI_CALLBACK TGL_Router(struct pci_dev *dev, unsigned int offset,
          unsigned long long wsize, ROUTER route)
  {
  void __iomem *mchmap;
  union {
      unsigned long long addr;
      struct {
          unsigned int low;
          unsigned int high;
      };
      struct
      {
          unsigned long long
          MCHBAREN    :  1-0,
          ReservedBits1   : 17-1,
          MCHBAR      : 39-17,
          ReservedBits2   : 64-39;
      };
  } mchbar;
  
  pci_read_config_dword(dev, offset    , &mchbar.low);
  pci_read_config_dword(dev, offset + 4, &mchbar.high);
  
  if (mchbar.MCHBAREN) {
      unsigned long long base = mchbar.addr & 0xffff0000;
      mchmap = ioremap(base, wsize);
      if (mchmap != NULL) {
          printk("base[%llx][%llx]map[%p]\n",
              mchbar.addr,base,mchmap);
          route(mchmap);
  
          iounmap(mchmap);
  
          return (0);
      } else
          return ((PCI_CALLBACK) -ENOMEM);
  } else
      return ((PCI_CALLBACK) -ENOMEM);
  }

static PCI_CALLBACK TGL_IMC(struct pci_dev dev) { / Some address offsets differ from Rocket Lake. */ pci_read_config_dword(dev, 0xe4, &PUBLIC(RO(Proc))->Uncore.Bus.SKL_Cap_A.value);

pci_read_config_dword(dev, 0xe8,
            &PUBLIC(RO(Proc))->Uncore.Bus.SKL_Cap_B.value);

pci_read_config_dword(dev, 0xec,
            &PUBLIC(RO(Proc))->Uncore.Bus.SKL_Cap_C.value);

SoC_SKL_VTD();

return (TGL_Router(dev, 0x48, 0x8000, Query_TGL_IMC));

}

[cyring]

I'm struggling to map the MCHBAR Whatever is the code: original Router() function and multiple changes in above function, like hard coded address 0xfedc0000 Kernel with that LENOVO ThinkPad E14 Gen 2 (BIOS R1EET36W 1.36) is reporting ACPI specification errors among BAR. Unfortunately BIOS can not be upgraded. I can't get MCHBAR of this Core i7-1165G7 to confirm IMC decoding.

EDIT

addr:mask[fedc0000:fffffffffffe0000]

Kernel change in [PATCH] perf/x86/intel/uncore: Fix oops when counting IMC uncore events on some TGL

Your help is welcomed.

[cyring]

Intel igen6_edac driver

EDIT: BAR address

mchbase=fedc0000
mchbar =fedd0000

[cyring]

Finally the IMC is showing up and it's not necessary the first controller !

The thing is that the Memory BAR is enabled on both controllers. I now need to find some registers with the activation state ...

[cyring]

The DIMM(s) may be not populated by channel but by controller, in first.

[cyring]

dmidecode -t memory

---

...
Memory Device
        Array Handle: 0x0001
        Error Information Handle: Not Provided
        Total Width: 64 bits
        Data Width: 64 bits
        Size: 16 GB
        Form Factor: SODIMM
        Set: None
        Locator: Controller1-ChannelA-DIMM0
        Bank Locator: BANK 0
        Type: DDR4
        Type Detail: Synchronous
        Speed: 3200 MT/s
        Manufacturer: Micron Technology
        Serial Number: 2E9D2675
        Asset Tag: None
        Part Number: 8ATF2G64HZ-3G2E1    
        Rank: 1
        Configured Memory Speed: 3200 MT/s
        Minimum Voltage: Unknown
        Maximum Voltage: Unknown
        Configured Voltage: 1.2 V
        Memory Technology: DRAM
        Memory Operating Mode Capability: Volatile memory
        Firmware Version: Not Specified
        Module Manufacturer ID: Bank 1, Hex 0x2C
        Module Product ID: Unknown
        Memory Subsystem Controller Manufacturer ID: Unknown
        Memory Subsystem Controller Product ID: Unknown
        Non-Volatile Size: None
        Volatile Size: 16 GB
        Cache Size: None
        Logical Size: None

[cyring]

• Capabilities

  TGL_Cap_A=f2006410
  TGL_Cap_B=10240008
  TGL_Cap_C=661820a
  TGL_Cap_E=1f9000
  MAD(CH0)=0
  MAD(CH1)=10000000

[cyring]

1. Loop over Controllers from 0 to 1

2. For each controller, loop over Channels from 0 to 1

3. For each channel, loop over DIMMs from 0 to 1

4. Remap the base address of the channel with a MMIO size of 0x10000. Kernel will warn about the BAR size but remapping is done.

5. The BAR appears enabled at bit 0 but its registers can be null. Thus the channel is not activated.

6. Proceed within the loops until the DIMM registers are different from zero. Meaning DIMM is populated.

https://github.com/cyring/CoreFreq/blob/ab278fc9fb01924397c7f19657fdf0772880dbed/corefreqk.c#L4811