Closed PJVol closed 3 years ago
Okay, first thing to change is the CPUID signature in file: https://github.com/cyring/CoreFreq/blob/ab278fc9fb01924397c7f19657fdf0772880dbed/corefreqk.h#L1490
with this:
#define _AMD_Zen3_CZN {.ExtFamily=0xa, .Family=0xF, .ExtModel=0x5, .Model=0x0}
Next rebuild and restart all.
Rebuit, but temp still missing, 0, zero. How to attach pictures here? Is it possible without 3rd party image hosting? Added picture in a forum where users learn some AI (for free) what the difference between truck and plane :)
Rebuit, but temp still missing, 0, zero. How to attach pictures here? Is it possible without 3rd party image hosting? Added picture in a forum where users learn some AI (for free) what the difference between truck and plane :)
You can now switch to the develop
branch where the CPUID fix is provided
I have checked Temperature code which should be processed the same as Vermeer (family 19h)
However it may have change for previous Zen2 register or a new register.
So let's try the followings in the develop
branch.
Query_AMD_Family_17h
at line:
https://github.com/cyring/CoreFreq/blob/3b70181da8f00a202901b2e434869d2bff669c53/corefreqk.c#L6291case AMD_Zen3_CZN:
( which will route Cesanne to the default case )
/* case AMD_Zen3_CZN: */
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Next browse to your picture file and click Preview
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For any source code and command outputs, just surround them with triple anti-quote
Temp is here, but is it Tctl? Who is SMBus Master 0, Nuvoton? Who can request temp via SB-TSI ? Does it poll amd's SBI?
Temp is here, but is it Tctl? Who is SMBus Master 0, Nuvoton? Who can request temp via SB-TSI ? Does it poll amd's SBI?
I have to back in AMD PPR specs to confirm you if SB-TSI or not ?
But my code is getting sensor value through an address register of the SMU.
Are you finally getting temperature with or without changing code in corefreqk.c
?
After commenting out Cezanne "case"
After commenting out Cezanne "case"
Thanks, I will reflect this in the next commit
Based on latest develop
branch, could you now change this line:
https://github.com/cyring/CoreFreq/blob/ee14fd3ba1a95c8bcdbe67a3953670a4e0f5b215/corefreqk.c#L6316
with:
PUBLIC(RO(Proc))->Features.HSMP_Capable = 1;
This will try to read bunch of SMU registers like the Power Limits PL1
PL2
and PPT
EDC
TDC
like my Matisse below:
Temp is here, but is it Tctl? Who is SMBus Master 0, Nuvoton? Who can request temp via SB-TSI ? Does it poll amd's SBI?
What is specify about offset register 0x00059800
https://github.com/cyring/CoreFreq/blob/c8f2a0e4215ecb5c27eea5d459422e43898e0178/amdmsr.h#L133
Provides the current control temperature (T ctl) after the slew-rate controls have been applied. CUR_TEMP. Reset: 000h. Provides current control temperature.
Have a look into the AMD Processor Programming Reference Repo link in CoreFreq wiki
Here is -s log vol@vol-H81M-S2VP:~/ryzen_smu/CoreFreq$ cat corefreq-s.log