Closed cyring closed 2 years ago
This is an unsolved issue about counters corruption after resuming processor from S3 (Suspend To Ram).
Looking into the UCC column, delta value of 18446744073709551615, the positive value of -1, let me think that the counter is stuck to reset.
18446744073709551615
-1
UCC is bound to the x86 register MSR_IA32_APERF https://github.com/cyring/CoreFreq/blob/07069d5c80acb48f55f1b944b1424f6109175f6e/corefreqk.c#L10548
MSR_IA32_APERF
The same test on a 5300U does not produce such issue!
Searching among the AMD specification updates has not revealed an errata.
Strangely, the effect tends to disappear over several periods and the MSR_IA32_APERF per CPU starts to count again, with occasional corruptions.
AMD/Matisse
This is an unsolved issue about counters corruption after resuming processor from S3 (Suspend To Ram).
Looking into the UCC column, delta value of
18446744073709551615, the positive value of-1, let me think that the counter is stuck to reset.UCC is bound to the x86 register
MSR_IA32_APERFhttps://github.com/cyring/CoreFreq/blob/07069d5c80acb48f55f1b944b1424f6109175f6e/corefreqk.c#L10548The same test on a 5300U does not produce such issue!
Searching among the AMD specification updates has not revealed an errata.
Before S3
After S3
Unexpected workaround
Strangely, the effect tends to disappear over several periods and the
MSR_IA32_APERFper CPU starts to count again, with occasional corruptions.