cyring / CoreFreq

CoreFreq : CPU monitoring and tuning software designed for 64-bit processors.
https://www.cyring.fr
GNU General Public License v2.0
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[SOLVED] Intel i5-12600K MSI Z690 PRO-A DDR5 #324

Closed SimonFair closed 2 years ago

SimonFair commented 2 years ago

image lspci.txt motherboard.txt lscpu.txt

dmidecode -t memory

`Handle 0x003A, DMI type 16, 23 bytes Physical Memory Array Location: System Board Or Motherboard Use: System Memory Error Correction Type: None Maximum Capacity: 256 GB Error Information Handle: Not Provided Number Of Devices: 4

Handle 0x003B, DMI type 17, 92 bytes Memory Device Array Handle: 0x003A Error Information Handle: Not Provided Total Width: Unknown Data Width: Unknown Size: No Module Installed Form Factor: Unknown Set: None Locator: Controller0-DIMMA1 Bank Locator: BANK 0 Type: Unknown Type Detail: None Speed: Unknown Manufacturer: Not Specified Serial Number: Not Specified Asset Tag: Not Specified Part Number: Not Specified Rank: Unknown Configured Memory Speed: Unknown Minimum Voltage: Unknown Maximum Voltage: Unknown Configured Voltage: Unknown Memory Technology: Memory Operating Mode Capability: None Firmware Version: Not Specified Module Manufacturer ID: Unknown Module Product ID: Unknown Memory Subsystem Controller Manufacturer ID: Unknown Memory Subsystem Controller Product ID: Unknown Non-Volatile Size: None Volatile Size: None Cache Size: None Logical Size: None

Handle 0x003C, DMI type 17, 92 bytes Memory Device Array Handle: 0x003A Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 16 GB Form Factor: DIMM Set: None Locator: Controller0-DIMMA2 Bank Locator: BANK 0 Type: Type Detail: Synchronous Speed: 4800 MT/s Manufacturer: Kingston Serial Number: 253018DD Asset Tag: 9876543210 Part Number: KF548C38-16
Rank: 1 Configured Memory Speed: 4800 MT/s Minimum Voltage: 1.1 V Maximum Voltage: 1.1 V Configured Voltage: 1.1 V Memory Technology: DRAM Memory Operating Mode Capability: Volatile memory Firmware Version: Not Specified Module Manufacturer ID: Bank 2, Hex 0x98 Module Product ID: Unknown Memory Subsystem Controller Manufacturer ID: Unknown Memory Subsystem Controller Product ID: Unknown Non-Volatile Size: None Volatile Size: 16 GB Cache Size: None Logical Size: None

Handle 0x003D, DMI type 17, 92 bytes Memory Device Array Handle: 0x003A Error Information Handle: Not Provided Total Width: Unknown Data Width: Unknown Size: No Module Installed Form Factor: Unknown Set: None Locator: Controller1-DIMMB1 Bank Locator: BANK 0 Type: Unknown Type Detail: None Speed: Unknown Manufacturer: Not Specified Serial Number: Not Specified Asset Tag: Not Specified Part Number: Not Specified Rank: Unknown Configured Memory Speed: Unknown Minimum Voltage: Unknown Maximum Voltage: Unknown Configured Voltage: Unknown Memory Technology: Memory Operating Mode Capability: Volatile memory Firmware Version: Not Specified Module Manufacturer ID: Unknown Module Product ID: Unknown Memory Subsystem Controller Manufacturer ID: Unknown Memory Subsystem Controller Product ID: Unknown Non-Volatile Size: None Volatile Size: None Cache Size: None Logical Size: None

Handle 0x003E, DMI type 17, 92 bytes Memory Device Array Handle: 0x003A Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 16 GB Form Factor: DIMM Set: None Locator: Controller1-DIMMB2 Bank Locator: BANK 0 Type: Type Detail: Synchronous Speed: 4800 MT/s Manufacturer: Kingston Serial Number: 24301922 Asset Tag: 9876543210 Part Number: KF548C38-16
Rank: 1 Configured Memory Speed: 4800 MT/s Minimum Voltage: 1.1 V Maximum Voltage: 1.1 V Configured Voltage: 1.1 V Memory Technology: DRAM Memory Operating Mode Capability: Volatile memory Firmware Version: Not Specified Module Manufacturer ID: Bank 2, Hex 0x98 Module Product ID: Unknown Memory Subsystem Controller Manufacturer ID: Unknown Memory Subsystem Controller Product ID: Unknown Non-Volatile Size: None Volatile Size: 16 GB Cache Size: None Logical Size: None `

cyring commented 2 years ago

@SimonFair Thank you very much.

Do you mind to post the outputs (in markdown style) of :

corefreq-cli -s -n -m -n -i 1 -n -c 1 -n -g 1 -n -C 1 -n -M
SimonFair commented 2 years ago
# corefreq-cli -s -n -m -n -i 1 -n -c 1 -n -g 1 -n -C 1 -n -M

Processor                                 [12th Gen Intel(R) Core(TM) i5-12600K]
|- Architecture                                                     [Alder Lake]
|- Vendor ID                                                      [GenuineIntel]
|- Microcode                                                        [0x0000001a]
|- Signature                                                           [  06_97]
|- Stepping                                                            [      2]
|- Online CPU                                                          [ 16/ 16]
|- Base Clock                                                          [ 99.619]
|- Frequency            (MHz)                      Ratio                        
                 Min    796.95                    <   8 >                       
                 Max   3685.89                    <  37 >                       
|- Factory                                                             [100.000]
                       3700                       [  37 ]                       
|- Performance                                                                  
   |- P-State                                                                   
                 TGT   6275.97                    <  63 >                       
   |- HWP                                                                       
                 Min   6275.97                    <  63 >                       
                 Max   6275.97                    <  63 >                       
                 TGT      AUTO                    <   0 >                       
|- Turbo Boost                                                         [ UNLOCK]
                  1C   4881.31                    <  49 >                       
                  2C   4881.31                    <  49 >                       
                  3C   4682.07                    <  47 >                       
                  4C   4682.07                    <  47 >                       
                  5C   4482.84                    <  45 >                       
                  6C   4482.84                    <  45 >                       
                  7C   4482.84                    <  45 >                       
                  8C   4482.84                    <  45 >                       
|- Uncore                                                              [ UNLOCK]
                 Min    796.95                    <   8 >                       
                 Max   4881.31                    <  49 >                       
|- TDP                                                           Level [  0:3  ]
   |- Programmable                                                     [ UNLOCK]
   |- Configuration                                                    [   LOCK]
   |- Turbo Activation                                                 [ UNLOCK]
             Nominal   3685.89                    [  37 ]                       
               Turbo      AUTO                    <   0 >                       

Instruction Set Extensions                                                      
|- 3DNow!/Ext [N/N]          ADX [Y]          AES [Y]  AVX/AVX2 [Y/Y] 
|- AVX512-F     [N]    AVX512-DQ [N]  AVX512-IFMA [N]   AVX512-PF [N] 
|- AVX512-ER    [N]    AVX512-CD [N]    AVX512-BW [N]   AVX512-VL [N] 
|- AVX512-VBMI  [N] AVX512-VBMI2 [N]  AVX512-VNMI [N]  AVX512-ALG [N] 
|- AVX512-VPOP  [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N] 
|- AVX512-BF16  [N]  BMI1/BMI2 [Y/Y]         CLWB [Y] CLFLUSH/O [Y/Y] 
|- CLAC-STAC    [Y]         CMOV [Y]    CMPXCHG8B [Y]  CMPXCHG16B [Y] 
|- F16C         [Y]          FPU [Y]         FXSR [Y]   LAHF-SAHF [Y] 
|- MMX/Ext    [Y/N] MON/MWAITX [Y/N]        MOVBE [Y]   PCLMULQDQ [Y] 
|- POPCNT       [Y]       RDRAND [Y]       RDSEED [Y]      RDTSCP [Y] 
|- SEP          [Y]          SHA [Y]          SSE [Y]        SSE2 [Y] 
|- SSE3         [Y]        SSSE3 [Y]  SSE4.1/4A [Y/N]      SSE4.2 [Y] 
|- SERIALIZE    [Y]      SYSCALL [Y]          SGX [N]       RDPID [Y] 

Features                                                                        
|- 1 GB Pages Support                                      1GB-PAGES   [Capable]
|- Advanced Configuration & Power Interface                     ACPI   [Capable]
|- Advanced Programmable Interrupt Controller                   APIC   [Capable]
|- APIC Timer Invariance                                        ARAT   [Capable]
|- Core Multi-Processing                                  CMP Legacy   [Missing]
|- L1 Data Cache Context ID                                  CNXT-ID   [Missing]
|- Direct Cache Access                                           DCA   [Missing]
|- Debugging Extension                                            DE   [Capable]
|- Debug Store & Precise Event Based Sampling               DS, PEBS   [Capable]
|- CPL Qualified Debug Store                                  DS-CPL   [Capable]
|- 64-Bit Debug Store                                         DTES64   [Capable]
|- Fast-String Operation                                Fast-Strings   [Capable]
|- Fused Multiply Add                                     FMA | FMA4   [Capable]
|- Hardware Lock Elision                                         HLE   [Missing]
|- Instruction Based Sampling                                    IBS   [Missing]
|- Instruction INVPCID                                       INVPCID   [Capable]
|- Long Mode 64 bits                                       IA64 | LM   [Capable]
|- LightWeight Profiling                                         LWP   [Missing]
|- Machine-Check Architecture                                    MCA   [Capable]
|- Memory Protection Extensions                                  MPX   [Missing]
|- Model Specific Registers                                      MSR   [Capable]
|- Memory Type Range Registers                                  MTRR   [Capable]
|- OS-Enabled Ext. State Management                          OSXSAVE   [Capable]
|- Physical Address Extension                                    PAE   [Capable]
|- Page Attribute Table                                          PAT   [Capable]
|- Pending Break Enable                                          PBE   [Capable]
|- Process Context Identifiers                                  PCID   [Capable]
|- Perfmon and Debug Capability                                 PDCM   [Capable]
|- Page Global Enable                                            PGE   [Capable]
|- Page Size Extension                                           PSE   [Capable]
|- 36-bit Page Size Extension                                  PSE36   [Capable]
|- Processor Serial Number                                       PSN   [Missing]
|- Resource Director Technology/PQE                            RDT-A   [Capable]
|- Resource Director Technology/PQM                            RDT-M   [Missing]
|- Restricted Transactional Memory                               RTM   [Missing]
|- Safer Mode Extensions                                         SMX   [Capable]
|- Self-Snoop                                                     SS   [Capable]
|- Supervisor-Mode Access Prevention                            SMAP   [Capable]
|- Supervisor-Mode Execution Prevention                         SMEP   [Capable]
|- Time Stamp Counter                                            TSC [Invariant]
|- Time Stamp Counter Deadline                          TSC-DEADLINE   [Capable]
|- TSX Force Abort MSR Register                            TSX-ABORT   [Missing]
|- TSX Suspend Load Address Tracking                       TSX-LDTRK   [Missing]
|- User-Mode Instruction Prevention                             UMIP   [Capable]
|- Virtual Mode Extension                                        VME   [Capable]
|- Virtual Machine Extensions                                    VMX   [Capable]
|- Extended xAPIC Support                                     x2APIC   [ x2APIC]
|- Execution Disable Bit Support                              XD-Bit   [Capable]
|- XSAVE/XSTOR States                                          XSAVE   [Capable]
|- xTPR Update Control                                          xTPR   [Capable]
Mitigation mechanisms                                                           
|- Indirect Branch Restricted Speculation                       IBRS   [ Enable]
|- Indirect Branch Prediction Barrier                           IBPB   [Capable]
|- Single Thread Indirect Branch Predictor                     STIBP   [Capable]
|- Speculative Store Bypass Disable                             SSBD   [Capable]
|- Writeback & invalidate the L1 data cache                L1D-FLUSH   [Capable]
|- Hypervisor - No flush L1D on VM entry            L1DFL_VMENTRY_NO   [ Enable]
|- Architectural - Buffer Overwriting                       MD-CLEAR   [Capable]
|- Architectural - Rogue Data Cache Load                     RDCL_NO   [ Enable]
|- Architectural - Enhanced IBRS                            IBRS_ALL   [ Enable]
|- Architectural - Return Stack Buffer Alternate                RSBA   [Capable]
|- Architectural - Speculative Store Bypass                   SSB_NO   [Capable]
|- Architectural - Microarchitectural Data Sampling           MDS_NO   [ Enable]
|- Architectural - TSX Asynchronous Abort                     TAA_NO   [ Enable]
|- Architectural - Page Size Change MCE               PSCHANGE_MC_NO   [ Enable]
|- Architectural - STLB QoS                                     STLB   [Capable]
|- Architectural - Functional Safety Island                     FuSa   [Capable]
|- Architectural - RSM in CPL0 only                              RSM   [Capable]
|- Architectural - Split Locked Access Exception                SPLA   [Capable]
|- Architectural - Snoop Filter QoS Mask                SNOOP_FILTER   [Capable]

Technologies                                                                    
|- Data Cache Unit                                                              
   |- L1 Prefetcher                                                L1 HW   < ON>
   |- L1 IP Prefetcher                                          L1 HW IP   < ON>
   |- L2 Prefetcher                                                L2 HW   < ON>
   |- L2 Line Prefetcher                                        L2 HW CL   < ON>
|- System Management Mode                                       SMM-Dual   [ ON]
|- Hyper-Threading                                                   HTT   [ ON]
|- SpeedStep                                                        EIST   < ON>
|- Dynamic Acceleration                                              IDA   [ ON]
|- Turbo Boost                                                     TURBO   < ON>
|- Energy Efficiency Optimization                                    EEO   <OFF>
|- Race To Halt Optimization                                         R2H   <OFF>
|- Watchdog Timer                                                    TCO   < ON>
|- Virtualization                                                    VMX   [ ON]
   |- I/O MMU                                                       VT-d   [ ON]
   |- Version                                                     [         4.0]
   |- Hypervisor                                                           [OFF]
   |- Vendor ID                                                   [         N/A]

Performance Monitoring                                                          
|- Version                                                        PM       [  5]
|- Counters:          General                   Fixed                           
|                     6 x 48 bits             3 x 48 bits                       
|- Enhanced Halt State                                           C1E       <OFF>
|- C1 Auto Demotion                                              C1A       < ON>
|- C3 Auto Demotion                                              C3A       <OFF>
|- C1 UnDemotion                                                 C1U       < ON>
|- C3 UnDemotion                                                 C3U       <OFF>
|- C6 Core Demotion                                              CC6       <OFF>
|- C6 Module Demotion                                            MC6       <OFF>
|- Legacy Frequency ID control                                   FID       [OFF]
|- Legacy Voltage ID control                                     VID       [OFF]
|- P-State Hardware Coordination Feedback                MPERF/APERF       [ ON]
|- Hardware-Controlled Performance States                        HWP       < ON>
   |- Capabilities      (MHz)                      Ratio                        
              Lowest     99.62                    [   1 ]                       
           Efficient   1295.04                    [  13 ]                       
          Guaranteed   4682.07                    [  47 ]                       
             Highest   6275.97                    [  63 ]                       
|- Hardware Duty Cycling                                         HDC       [OFF]
|- Package C-States                                                             
   |- Configuration Control                                   CONFIG   [   LOCK]
   |- Lowest C-State                                           LIMIT   <     C0>
   |- I/O MWAIT Redirection                                  IOMWAIT   <Disable>
   |- Max C-State Inclusion                                    RANGE   <     C1>
|- Core C-States                                                                
   |- C-States Base Address                                      BAR   [ 0x1814]
|- MONITOR/MWAIT                                                                
   |- State index:    #0    #1    #2    #3    #4    #5    #6    #7              
   |- Sub C-State:     0     2     0     2     0     1     0     1              
|- Core Cycles                                                         [Capable]
|- Instructions Retired                                                [Capable]
|- Reference Cycles                                                    [Capable]
|- Last Level Cache References                                         [Capable]
|- Last Level Cache Misses                                             [Capable]
|- Branch Instructions Retired                                         [Capable]
|- Branch Mispredicts Retired                                          [Capable]
|- Top-down slots Counter                                              [Capable]

Power, Current & Thermal                                                        
|- Clock Modulation                                             ODCM   <Disable>
   |- DutyCycle                                                        [  0.00%]
|- Power Management                                         PWR MGMT   [   LOCK]
   |- Energy Policy                                        Bias Hint   [      0]
   |- Energy Policy                                          HWP EPP   <      0>
|- Temperature Offset:Junction                                 TjMax [  0:100 C]
|- Digital Thermal Sensor                                        DTS   [Capable]
|- Power Limit Notification                                      PLN   [Capable]
|- Package Thermal Management                                    PTM   [Capable]
|- Thermal Monitor 1                                             TM1   [ Enable]
|- Thermal Monitor 2                                             TM2   [Capable]
|- Thermal Design Power                                          TDP   [  125 W]
   |- Minimum Power                                              Min   [Missing]
   |- Maximum Power                                              Max   [Missing]
|- Thermal Design Power                                      Package   < Enable>
   |- Power Limit (56 sec)                                       PL1   < 4095 W>
   |- Power Limit (1 sec)                                        PL2   < 4095 W>
|- Thermal Design Power                                         Core   <Disable>
   |- Power Limit                                                PL1   [Missing]
|- Thermal Design Power                                       Uncore   <Disable>
   |- Power Limit                                                PL1   [Missing]
|- Thermal Design Power                                         DRAM   <Disable>
   |- Power Limit                                                PL1   [Missing]
|- Thermal Design Power                                     Platform   <Disable>
   |- Power Limit                                                PL1   [Missing]
   |- Power Limit                                                PL2   [Missing]
|- Electrical Design Current                                     EDC   [Missing]
|- Thermal Design Current                                        TDC   [Missing]
|- Core Thermal Point                                                           
   |- DTS Threshold #1                                     Threshold   [Missing]
   |- DTS Threshold #2                                     Threshold   [Missing]
|- Package Thermal Point                                                        
   |- DTS Threshold #1                                     Threshold   [Missing]
   |- DTS Threshold #2                                     Threshold   [Missing]
|- Units                                                                        
   |- Power                                               watt   [  0.125000000]
   |- Energy                                             joule   [  0.000061035]
   |- Window                                            second   [  0.000976562]

CPU Pkg  Apic  Core/Thread  Caches      (w)rite-Back (i)nclusive              
 #   ID   ID    ID     ID  L1-Inst Way  L1-Data Way      L2  Way      L3  Way 
000:BSP    0     0      0    32768  8     49152 12   1310720 10  20971520 10  
001:  0    1     0      1    32768  8     49152 12   1310720 10  20971520 10  
002:  0    8     4      0    32768  8     49152 12   1310720 10  20971520 10  
003:  0    9     4      1    32768  8     49152 12   1310720 10  20971520 10  
004:  0   16     8      0    32768  8     49152 12   1310720 10  20971520 10  
005:  0   17     8      1    32768  8     49152 12   1310720 10  20971520 10  
006:  0   24    12      0    32768  8     49152 12   1310720 10  20971520 10  
007:  0   25    12      1    32768  8     49152 12   1310720 10  20971520 10  
008:  0   32    16      0    32768  8     49152 12   1310720 10  20971520 10  
009:  0   33    16      1    32768  8     49152 12   1310720 10  20971520 10  
010:  0   40    20      0    32768  8     49152 12   1310720 10  20971520 10  
011:  0   41    20      1    32768  8     49152 12   1310720 10  20971520 10  
012:  0   56    28      0    65536  8     32768  8   2097152 16  20971520 10  
013:  0   58    29      0    65536  8     32768  8   2097152 16  20971520 10  
014:  0   60    30      0    65536  8     32768  8   2097152 16  20971520 10  
015:  0   62    31      0    65536  8     32768  8   2097152 16  20971520 10  

CPU     IPS            IPC            CPI
000     0.021134/s     1.749746/c     0.571511/i
001     0.006494/s     1.090245/c     0.917225/i
002     0.000020/s     0.164522/c     6.078215/i
003     0.000018/s     0.177548/c     5.632292/i
004     0.000019/s     0.151442/c     6.603189/i
005     0.000018/s     0.165815/c     6.030834/i
006     0.000020/s     0.161894/c     6.176897/i
007     0.000018/s     0.180764/c     5.532078/i
008     0.000022/s     0.120980/c     8.265806/i
009     0.000018/s     0.128967/c     7.753901/i
010     0.000024/s     0.124876/c     8.007943/i
011     0.000032/s     0.149384/c     6.694136/i
012     0.006346/s     0.906504/c     1.103139/i
013     0.006930/s     1.008481/c     0.991590/i
014     0.002223/s     0.568261/c     1.759754/i
015     0.000689/s     0.364669/c     2.742216/i

CPU Freq(MHz) Ratio  Turbo  C0(%)  C1(%)  C3(%)  C6(%)  C7(%)  Min TMP:TS  Max
000   18.54 ( 0.19)   0.50   0.42  13.49   0.00  86.09   0.00  21 / 26:74 / 53
001   19.66 ( 0.20)   0.53   0.42  13.49   0.00  86.09   0.00  21 / 26:74 / 53
002    0.54 ( 0.01)   0.01   0.01   0.00   0.00  99.99   0.00  21 / 24:76 / 28
003    0.54 ( 0.01)   0.01   0.01   0.00   0.00  99.99   0.00  21 / 24:76 / 28
004    0.48 ( 0.00)   0.01   0.01   0.00   0.00  99.99   0.00  21 / 23:77 / 36
005    0.57 ( 0.01)   0.02   0.01   0.00   0.00  99.99   0.00  21 / 23:77 / 36
006    0.48 ( 0.00)   0.01   0.01   0.00   0.00  99.99   0.00  21 / 25:75 / 29
007    0.49 ( 0.00)   0.01   0.01   0.00   0.00  99.99   0.00  21 / 25:75 / 29
008    0.88 ( 0.01)   0.02   0.02   0.01   0.00  99.97   0.00  24 / 28:72 / 32
009    0.89 ( 0.01)   0.02   0.02   0.01   0.00  99.97   0.00  24 / 28:72 / 32
010    0.76 ( 0.01)   0.02   0.02   0.00   0.00  99.98   0.00  23 / 25:75 / 30
011    0.76 ( 0.01)   0.02   0.02   0.00   0.00  99.98   0.00  23 / 25:75 / 30
012   11.57 ( 0.12)   0.31   0.35   6.59   0.00  93.06   0.00  24 / 28:72 / 37
013   14.72 ( 0.15)   0.40   0.44   4.57   0.00  94.99   0.00  24 / 28:72 / 37
014    6.83 ( 0.07)   0.19   0.21   3.21   0.00  96.58   0.00  24 / 28:72 / 37
015    4.20 ( 0.04)   0.11   0.14   3.39   0.00  96.47   0.00  24 / 28:72 / 37

    Averages:        Turbo  C0(%)  C1(%)  C3(%)  C6(%)  C7(%)    TjMax:    Pkg:
                      0.14   0.13   2.80   0.00  97.07   0.00     100 C    28 C

                Cycles          State(%)
PC02                     0         0.00
PC03                     0         0.00
PC04                     0         0.00
PC06                     0         0.00
PC07                     0         0.00
PC08                     0         0.00
PC09                     0         0.00
PC10                     0         0.00
MC6                      0         0.00
PTSC            3686331704
UNCORE                   0

CPU Freq(MHz) VID  Vcore  TMP(C)    Accumulator       Energy(J)     Power(W)
000   38.91 10559  1.2889   26  000000000000000000    0.000000000   0.000000000
001   72.52     0  0.0000   26  000000000000000000    0.000000000   0.000000000
002    0.48     0  0.0000   24  000000000000000000    0.000000000   0.000000000
003    0.47     0  0.0000   24  000000000000000000    0.000000000   0.000000000
004    0.49     0  0.0000   24  000000000000000000    0.000000000   0.000000000
005    0.61     0  0.0000   24  000000000000000000    0.000000000   0.000000000
006    0.54     0  0.0000   24  000000000000000000    0.000000000   0.000000000
007    0.54     0  0.0000   24  000000000000000000    0.000000000   0.000000000
008    0.68     0  0.0000   27  000000000000000000    0.000000000   0.000000000
009    1.01     0  0.0000   27  000000000000000000    0.000000000   0.000000000
010    0.71     0  0.0000   25  000000000000000000    0.000000000   0.000000000
011    0.71     0  0.0000   25  000000000000000000    0.000000000   0.000000000
012   16.82     0  0.0000   28  000000000000000000    0.000000000   0.000000000
013   11.94     0  0.0000   28  000000000000000000    0.000000000   0.000000000
014   11.49     0  0.0000   28  000000000000000000    0.000000000   0.000000000
015    8.64     0  0.0000   28  000000000000000000    0.000000000   0.000000000

             Package       Cores         Uncore        Memory        Platform
Energy(J):   6.481018066   5.051940918   0.000000000   0.000000000   0.000000000
Power(W) :   6.481018066   5.051940918   0.000000000   0.000000000   0.000000000

                             Intel Z690  [7A84]                            
Controller #0                                                Dual Channel  
 Bus Rate  8000 MT/s      Bus Speed 7971 MT/s          DDR5 Speed 3199 MHz 

 Cha    CL  RCD   RP  RAS RRDS RRDL  FAW   WR RTPr WTPr  CWL CKE  CMD   B2B
  #0    38   38   38    0    0    0    04294967256   17    0   36  18   2T     0
  #1    38   38   38    0    0    0    04294967256   17    0   36  18   2T     0
      sgRR dgRR drRR ddRR      sgRW dgRW drRW ddRW      sgWR dgWR drWR ddWR
  #0    32   24    4   73       140    8   14   14        18    9    5   11
  #1    32   24    4   73       140    8   14   14        18    9    5   11
      sgWW dgWW drWW ddWW                         CPDED      REFI  RFC  ECC
  #0    70  104   48   24                            12      4680  383    0
  #1    70  104   48   24                            12      4680  383    0

 DIMM Geometry for channel #0                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0                                                                  
       #1     8    1     65536       512           8192                    
 DIMM Geometry for channel #1                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0                                                                  
       #1     8    1     65536       512           8192                    

Controller #1                                                Dual Channel  
 Bus Rate  8000 MT/s      Bus Speed 7971 MT/s          DDR5 Speed 3199 MHz 

 Cha    CL  RCD   RP  RAS RRDS RRDL  FAW   WR RTPr WTPr  CWL CKE  CMD   B2B
  #0    38   38   38    0    0    0    04294967256   17    0   36  18   2T     0
  #1    38   38   38    0    0    0    04294967256   17    0   36  18   2T     0
      sgRR dgRR drRR ddRR      sgRW dgRW drRW ddRW      sgWR dgWR drWR ddWR
  #0    32   24    4   73       140    8   14   14        18    9    5   11
  #1    32   24    4   73       140    8   14   14        18    9    5   11
      sgWW dgWW drWW ddWW                         CPDED      REFI  RFC  ECC
  #0    70  104   48   24                            12      4680  383    0
  #1    70  104   48   24                            12      4680  383    0

 DIMM Geometry for channel #0                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0                                                                  
       #1     8    1     65536       512           8192                    
 DIMM Geometry for channel #1                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0                                                                  
       #1     8    1     65536       512           8192                    
cyring commented 2 years ago

Hello,

Could you give a try to the branch develop I would like to be sure it works as good as tests with i7-12700K in issue #323

Screenshots will be helpful. Thank you.

SimonFair commented 2 years ago

Yes it is working. Let me know if there are additional screen prints you would like to see.

image

image

image

cyring commented 2 years ago

Yes it is working. Let me know if there are additional screen prints you would like to see.

image

Thanks a lot.

This screenshot, I'm observing that i5-12600K Pcore is sleeping down to C6 C-state whereas i7-12700K is able at C7 (as seen in issue #323) It might be due either by the CPU-Idle governing your Linux (and MWAIT in used) or a particularity of i5 or any BIOS choice.

SimonFair commented 2 years ago

Thanks will talk to ich777 to see if he has done anything specific on his system. I know our motherboards are different and I had to revert my BIOS of the latest beta as having issues booting from USBs

cyring commented 2 years ago

Thanks for this issue.

cyring commented 2 years ago

@SimonFair Hello

I would like to check for non-regression on Alder lake, could you give a try to the develop branch ?

Please provide the output of corefreq-cli -s -n -m -n -M -n -B -n -k -n -C 1 -c 1

SimonFair commented 2 years ago

Hi I normally use the package as compiled by @ich777 so not sure how easy it will be able for me to test.

cyring commented 2 years ago

Hi I normally use the package as compiled by @ich777 so not sure how easy it will be able for me to test.

agree

ich777 commented 2 years ago

I can compile a package from the develop branch if you want to tomorrow @SimonFair, on what Unraid version are you currently?

SimonFair commented 2 years ago

@ich777 rc3p2

SimonFair commented 2 years ago

corefreq.txt as requested

cyring commented 2 years ago

corefreq.txt as requested

Nice, thank you.

It looks like 3 feature states are missing:

I'm not sure if the last two are part of the architecture ?

EDIT: previously TCO was detected. So I believe it has this time be deactivated in BIOS ?