cyring
commented
2 years ago Hello,
Can you post (Markdown formatted) the output of corefreq-cli -s -m -M -v
Closed Chlorophytus closed 2 years ago
cyring
commented
2 years ago Hello,
Can you post (Markdown formatted) the output of corefreq-cli -s -m -M -v
cyring
commented
2 years ago Also edit the driver source file at: https://github.com/cyring/CoreFreq/blob/20426b669d2da01f93cab8dd208ac3c476333aa7/corefreqk.c#L5870
and replace with 2 the umc_max to query as below:
static PCI_CALLBACK AMD_DataFabric_Starship(struct pci_dev *pdev)
{
return AMD_17h_DataFabric(pdev, 2);
}Rebuild (make clean all) , reload and test UMC again
Chlorophytus
commented
2 years ago Hello,
Can you post (Markdown formatted) the output of
corefreq-cli -s -m -M -v
accelshark@Funbox ~ % corefreq-cli -s -m -M -v
Processor [AMD Ryzen Threadripper 3960X 24-Core Processor]
|- Architecture [Zen2/Castle Peak]
|- Vendor ID [AuthenticAMD]
|- Firmware [ 36.34.0-2]
|- Microcode [0x08301055]
|- Signature [ 8F_31]
|- Stepping [ 0]
|- Online CPU [ 48/ 48]
|- Base Clock [100.000]
|- Frequency (MHz) Ratio
Min 2200.04 < 22 >
Max 3800.06 < 38 >
|- Factory [100.000]
3800 [ 38 ]
|- Performance
|- P-State
TGT 3800.06 < 38 >
|- Turbo Boost [ UNLOCK]
XFR 4600.07 [ 46 ]
CPB 4500.07 [ 45 ]
1C 2800.05 < 28 >
2C 2200.04 < 22 >
|- Uncore [ LOCK]
|- TDP Level [ 0:0 ]
|- Programmable [ LOCK]
Instruction Set Extensions
|- 3DNow!/Ext [N/N] ADX [Y] AES [Y] AVX/AVX2 [Y/Y]
|- AVX512-F [N] AVX512-DQ [N] AVX512-IFMA [N] AVX512-PF [N]
|- AVX512-ER [N] AVX512-CD [N] AVX512-BW [N] AVX512-VL [N]
|- AVX512-VBMI [N] AVX512-VBMI2 [N] AVX512-VNNI [N] AVX512-ALG [N]
|- AVX512-VPOP [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N]
|- AVX512-BF16 [N] AVX-VNNI-VEX [N] AVX-FP128 [N] AVX-FP256 [Y]
|- BMI1/BMI2 [Y/Y] CLWB [Y] CLFLUSH [Y] CLFLUSH-OPT [Y]
|- CLAC-STAC [Y] CMOV [Y] CMPXCHG8B [Y] CMPXCHG16B [Y]
|- F16C [Y] FPU [Y] FXSR [Y] LAHF-SAHF [Y]
|- MMX/Ext [Y/Y] MON/MWAITX [Y/Y] MOVBE [Y] PCLMULQDQ [Y]
|- POPCNT [Y] RDRAND [Y] RDSEED [Y] RDTSCP [Y]
|- SEP [Y] SHA [Y] SSE [Y] SSE2 [Y]
|- SSE3 [Y] SSSE3 [Y] SSE4.1/4A [Y/Y] SSE4.2 [Y]
|- SERIALIZE [N] SYSCALL [Y] RDPID [N] UMIP [N]
Features
|- 1 GB Pages Support 1GB-PAGES [Capable]
|- 100 MHz multiplier Control 100MHzSteps [Missing]
|- Advanced Configuration & Power Interface ACPI [Capable]
|- Advanced Programmable Interrupt Controller APIC [Capable]
|- APIC Timer Invariance ARAT [Capable]
|- Core Multi-Processing CMP Legacy [Capable]
|- L1 Data Cache Context ID CNXT-ID [Missing]
|- Collaborative Processor Performance Control CPPC [Missing]
|- Direct Cache Access DCA [Missing]
|- Debugging Extension DE [Capable]
|- Debug Store & Precise Event Based Sampling DS, PEBS [Missing]
|- CPL Qualified Debug Store DS-CPL [Missing]
|- 64-Bit Debug Store DTES64 [Missing]
|- Fast Short REP MOVSB FSRM [Missing]
|- Fast-String Operation ERMS [Missing]
|- Fused Multiply Add FMA | FMA4 [Capable]
|- Hardware Lock Elision HLE [Missing]
|- Hardware P-state control HwP [Capable]
|- Instruction Based Sampling IBS [Capable]
|- Instruction INVLPGB INVLPGB [Missing]
|- Instruction INVPCID INVPCID [Missing]
|- Long Mode 64 bits IA64 | LM [Capable]
|- LightWeight Profiling LWP [Missing]
|- Memory Bandwidth Enforcement MBE [Capable]
|- Machine-Check Architecture MCA [Capable]
|- Instruction MCOMMIT MCOMMIT [Capable]
|- Memory Protection Extensions MPX [Missing]
|- Model Specific Registers MSR [Capable]
|- Memory Type Range Registers MTRR [Capable]
|- No-Execute Page Protection NX [Capable]
|- OS-Enabled Ext. State Management OSXSAVE [Capable]
|- Physical Address Extension PAE [Capable]
|- Page Attribute Table PAT [Capable]
|- Pending Break Enable PBE [Missing]
|- Process Context Identifiers PCID [Missing]
|- Perfmon and Debug Capability PDCM [Missing]
|- Page Global Enable PGE [Capable]
|- Page Size Extension PSE [Capable]
|- 36-bit Page Size Extension PSE36 [Capable]
|- Processor Serial Number PSN [Missing]
|- Resource Director Technology/PQE RDT-A [Capable]
|- Resource Director Technology/PQM RDT-M [Capable]
|- Read Processor Register at User level RDPRU [Capable]
|- Restricted Transactional Memory RTM [Missing]
|- Safer Mode Extensions SMX [Missing]
|- Self-Snoop SS [Missing]
|- Supervisor-Mode Access Prevention SMAP [Capable]
|- Supervisor-Mode Execution Prevention SMEP [Capable]
|- Time Stamp Counter TSC [Invariant]
|- Time Stamp Counter Deadline TSC-DEADLINE [Missing]
|- TSX Force Abort MSR Register TSX-ABORT [Missing]
|- TSX Suspend Load Address Tracking TSX-LDTRK [Missing]
|- User-Mode Instruction Prevention UMIP [Missing]
|- Virtual Mode Extension VME [Capable]
|- Virtual Machine Extensions VMX [Missing]
|- Extended xAPIC Support x2APIC [ xAPIC]
|- XSAVE/XSTOR States XSAVE [Capable]
|- xTPR Update Control xTPR [Missing]
Mitigation mechanisms
|- Indirect Branch Restricted Speculation IBRS [Missing]
|- IBRS Always-On preferred by processor [Missing]
|- IBRS preferred over software solution [Capable]
|- IBRS provides same speculation limits [Capable]
|- Indirect Branch Prediction Barrier IBPB [Capable]
|- Single Thread Indirect Branch Predictor STIBP [ Enable]
|- Speculative Store Bypass Disable SSBD [Capable]
|- SSBD use VIRT SPEC_CTRL register [Missing]
|- SSBD not needed on this processor [Missing]
|- Architectural - Predictive Store Forwarding PSFD [Missing]
Technologies
|- Data Cache Unit
|- L1 Prefetcher L1 HW < ON>
|- L2 Prefetcher L2 HW < ON>
|- System Management Mode SMM-Lock [ ON]
|- Simultaneous Multithreading SMT [ ON]
|- PowerNow! CnQ [OFF]
|- Core C-States CCx [ ON]
|- Core Performance Boost CPB < ON>
|- Watchdog Timer WDT < ON>
|- Virtualization SVM [ ON]
|- I/O MMU AMD-V [ ON]
|- Version [ 0.1]
|- Hypervisor [OFF]
|- Vendor ID [ N/A]
Performance Monitoring
|- Version PM [N/A]
|- Counters: General Fixed
| { 6, 6, 4 } x 48 bits 3 x 64 bits
|- Enhanced Halt State C1E <OFF>
|- C2 UnDemotion C2U <OFF>
|- C3 UnDemotion C3U < ON>
|- Core C6 State CC6 <OFF>
|- Package C6 State PC6 < ON>
|- Legacy Frequency ID control FID [OFF]
|- Legacy Voltage ID control VID [OFF]
|- P-State Hardware Coordination Feedback MPERF/APERF [ ON]
|- Collaborative Processor Performance Control CPPC [N/A]
|- Core C-States
|- C-States Base Address BAR [ 0x813 ]
|- MONITOR/MWAIT
|- State index: #0 #1 #2 #3 #4 #5 #6 #7
|- Sub C-State: 1 1 0 0 0 0 0 0
|- Core Cycles [Capable]
|- Instructions Retired [Capable]
|- Reference Cycles [Capable]
|- Last Level Cache References [Capable]
|- Global Time Stamp Counter [Missing]
|- Data Fabric Performance Counter [Capable]
|- Core Performance Counter [Capable]
Power, Current & Thermal
|- Temperature Offset:Junction TjMax [ 49: 12 C]
|- CPPC Energy Preference CPPC [Missing]
|- Digital Thermal Sensor DTS [Capable]
|- Power Limit Notification PLN [Missing]
|- Package Thermal Management PTM [Missing]
|- Thermal Monitor 1 TTP [ Enable]
|- Thermal Monitor 2 HTC [ Enable]
|- Thermal Design Power TDP [ 480 W]
|- Minimum Power Min [ 104 W]
|- Maximum Power Max [ 258 W]
|- Thermal Design Power Package < Enable>
|- Power Limit PL1 < 280 W>
|- Time Window TW1 < 0 ns>
|- Power Limit PL2 < 1000 W>
|- Time Window TW2 < 0 ns>
|- Thermal Design Power Core [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 0 ns]
|- Thermal Design Power Uncore [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 0 ns]
|- Thermal Design Power DRAM [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 0 ns]
|- Thermal Design Power Platform [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 0 ns]
|- Power Limit PL2 [ 0 W]
|- Time Window TW2 [ 0 ns]
|- Package Power Tracking PPT [ 4 W]
|- Electrical Design Current EDC [ 384 A]
|- Thermal Design Current TDC [ 96 A]
|- Core Thermal Point
|- Package Thermal Point
|- Thermal Monitor Trip Limit [ 115 C]
|- HTC Temperature Limit Limit [ 127 C]
|- HTC Temperature Hysteresis Threshold [ 2 C]
|- Units
|- Power watt [ 0.125000000]
|- Energy joule [ 0.000015259]
|- Window second [ 0.000976562]
CPU Pkg Apic Core/Thread Caches (w)rite-Back (i)nclusive
# ID ID CCD CCX ID/ID L1-Inst Way L1-Data Way L2 Way L3 Way
000:BSP 0 0 0 0 0 32 8 32 8 512 8 i 131072 16w
001: 0 2 0 0 1 0 32 8 32 8 512 8 i 131072 16w
002: 0 4 0 0 2 0 32 8 32 8 512 8 i 131072 16w
003: 0 8 0 1 4 0 32 8 32 8 512 8 i 131072 16w
004: 0 10 0 1 5 0 32 8 32 8 512 8 i 131072 16w
005: 0 12 0 1 6 0 32 8 32 8 512 8 i 131072 16w
006: 0 16 2 2 8 0 32 8 32 8 512 8 i 131072 16w
007: 0 18 2 2 9 0 32 8 32 8 512 8 i 131072 16w
008: 0 20 2 2 10 0 32 8 32 8 512 8 i 131072 16w
009: 0 24 2 3 12 0 32 8 32 8 512 8 i 131072 16w
010: 0 26 2 3 13 0 32 8 32 8 512 8 i 131072 16w
011: 0 28 2 3 14 0 32 8 32 8 512 8 i 131072 16w
012: 0 32 4 4 16 0 32 8 32 8 512 8 i 131072 16w
013: 0 34 4 4 17 0 32 8 32 8 512 8 i 131072 16w
014: 0 36 4 4 18 0 32 8 32 8 512 8 i 131072 16w
015: 0 40 4 5 20 0 32 8 32 8 512 8 i 131072 16w
016: 0 42 4 5 21 0 32 8 32 8 512 8 i 131072 16w
017: 0 44 4 5 22 0 32 8 32 8 512 8 i 131072 16w
018: 0 48 6 6 24 0 32 8 32 8 512 8 i 131072 16w
019: 0 50 6 6 25 0 32 8 32 8 512 8 i 131072 16w
020: 0 52 6 6 26 0 32 8 32 8 512 8 i 131072 16w
021: 0 56 6 7 28 0 32 8 32 8 512 8 i 131072 16w
022: 0 58 6 7 29 0 32 8 32 8 512 8 i 131072 16w
023: 0 60 6 7 30 0 32 8 32 8 512 8 i 131072 16w
024: 0 1 0 0 0 1 32 8 32 8 512 8 i 131072 16w
025: 0 3 0 0 1 1 32 8 32 8 512 8 i 131072 16w
026: 0 5 0 0 2 1 32 8 32 8 512 8 i 131072 16w
027: 0 9 0 1 4 1 32 8 32 8 512 8 i 131072 16w
028: 0 11 0 1 5 1 32 8 32 8 512 8 i 131072 16w
029: 0 13 0 1 6 1 32 8 32 8 512 8 i 131072 16w
030: 0 17 2 2 8 1 32 8 32 8 512 8 i 131072 16w
031: 0 19 2 2 9 1 32 8 32 8 512 8 i 131072 16w
032: 0 21 2 2 10 1 32 8 32 8 512 8 i 131072 16w
033: 0 25 2 3 12 1 32 8 32 8 512 8 i 131072 16w
034: 0 27 2 3 13 1 32 8 32 8 512 8 i 131072 16w
035: 0 29 2 3 14 1 32 8 32 8 512 8 i 131072 16w
036: 0 33 4 4 16 1 32 8 32 8 512 8 i 131072 16w
037: 0 35 4 4 17 1 32 8 32 8 512 8 i 131072 16w
038: 0 37 4 4 18 1 32 8 32 8 512 8 i 131072 16w
039: 0 41 4 5 20 1 32 8 32 8 512 8 i 131072 16w
040: 0 43 4 5 21 1 32 8 32 8 512 8 i 131072 16w
041: 0 45 4 5 22 1 32 8 32 8 512 8 i 131072 16w
042: 0 49 6 6 24 1 32 8 32 8 512 8 i 131072 16w
043: 0 51 6 6 25 1 32 8 32 8 512 8 i 131072 16w
044: 0 53 6 6 26 1 32 8 32 8 512 8 i 131072 16w
045: 0 57 6 7 28 1 32 8 32 8 512 8 i 131072 16w
046: 0 59 6 7 29 1 32 8 32 8 512 8 i 131072 16w
047: 0 61 6 7 30 1 32 8 32 8 512 8 i 131072 16w
Zen UMC [1490]
Controller #0 Dual Channel
Bus Rate 0 MHz Bus Speed 0 MHz DRAM Speed 0 MHz
Cha CL RCD RP RAS RRD RFC WR RTPr WTPr FAW B2B CWL CMD REFI
#0 0 0 0 0 0 0 0 0 0 0 0 0 1T 0
#1 0 0 0 0 0 0 0 0 0 0 0 0 1T 0
ddWR drWR srWR ddRW drRW srRW ddRR drRR srRR ddWW drWW srWW CKE ECC
#0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
#1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1
CoreFreq. Copyright (C) 2015-2022 CYRIL INGENIERIE
Usage: corefreq-cli [-Option <argument>] [-Command <argument>]
Interface options
-Oa Absolute frequency
-Ok Memory unit in kilobyte
-Om Memory unit in megabyte
-Og Memory unit in gigabyte
-OF Temperature in Fahrenheit
-OJ # SMBIOS string index number
-OE # Color theme index number
-OY Show Secret Data
Command options
-t <v> Show Top (default) with optional <v>iew:
{ frequency, instructions, core, idle, package, tasks,
interrupts, sensors, voltage, power, slices, custom }
-d Show Dashboard
-C <#> Monitor Sensors
-V <#> Monitor Voltage
-W <#> Monitor Power
-g <#> Monitor Package
-c <#> Monitor Counters
-i <#> Monitor Instructions
-s Print System Information
-j Print System Information (json-encoded)
-M Print Memory Controller
-R Print System Registers
-m Print Topology
-u Print CPUID
-B Print SMBIOS
-k Print Kernel
-n New line
-h Print out this message
-v Print the version number
Exit status:
0 SUCCESS Successful execution
3 CMD_SYNTAX Command syntax error
4 SHM_FILE Shared memory file error
5 SHM_MMAP Shared memory mapping error
6 PERM_ERR Execution not permitted
7 MEM_ERR Memory operation error
8 EXEC_ERR General execution error
9 SYS_CALL System call error
Report bugs to labs[at]cyring.frAlso edit the driver source file at:
https://github.com/cyring/CoreFreq/blob/20426b669d2da01f93cab8dd208ac3c476333aa7/corefreqk.c#L5870
and replace with
2the umc_max to query as below:static PCI_CALLBACK AMD_DataFabric_Starship(struct pci_dev *pdev) { return AMD_17h_DataFabric(pdev, 2); }Rebuild (
make clean all) , reload and test UMC again
The UMC is still unrecognized and reads dual channel. I didn't update something on the PKGBUILD, hold on.
cyring
commented
2 years ago If 2 does not give better results, try 4
Chlorophytus
commented
2 years ago If
2does not give better results, try4
I tried compiling it outside of the PKGBUILD. Neither 2 nor 4 works.
Chlorophytus
commented
2 years ago Does this have anything to do with the problem, saw it on dmesg.
[ 144.162745] CoreFreq: AMD_17h_DataFabric() Break UMC(1) probing @ PCI(0x0:0x0:0xc8)Does this have anything to do with the problem, saw it on
dmesg.[ 144.162745] CoreFreq: AMD_17h_DataFabric() Break UMC(1) probing @ PCI(0x0:0x0:0xc8)
I need to confirm the Data Fabric PCI Id.
Can you post the output of lspci -nn
Chlorophytus
commented
2 years ago Does this have anything to do with the problem, saw it on
dmesg.[ 144.162745] CoreFreq: AMD_17h_DataFabric() Break UMC(1) probing @ PCI(0x0:0x0:0xc8)I need to confirm the Data Fabric PCI Id. Can you post the output of
lspci -nn
00:00.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Root Complex [1022:1480]
00:00.2 IOMMU [0806]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse IOMMU [1022:1481]
00:01.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482]
00:01.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse GPP Bridge [1022:1483]
00:02.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482]
00:03.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482]
00:04.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482]
00:05.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482]
00:07.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482]
00:07.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Internal PCIe GPP Bridge 0 to bus[E:B] [1022:1484]
00:08.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482]
00:08.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Internal PCIe GPP Bridge 0 to bus[E:B] [1022:1484]
00:14.0 SMBus [0c05]: Advanced Micro Devices, Inc. [AMD] FCH SMBus Controller [1022:790b] (rev 61)
00:14.3 ISA bridge [0601]: Advanced Micro Devices, Inc. [AMD] FCH LPC Bridge [1022:790e] (rev 51)
00:18.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship Device 24; Function 0 [1022:1490]
00:18.1 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship Device 24; Function 1 [1022:1491]
00:18.2 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship Device 24; Function 2 [1022:1492]
00:18.3 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship Device 24; Function 3 [1022:1493]
00:18.4 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship Device 24; Function 4 [1022:1494]
00:18.5 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship Device 24; Function 5 [1022:1495]
00:18.6 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship Device 24; Function 6 [1022:1496]
00:18.7 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship Device 24; Function 7 [1022:1497]
01:00.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD/ATI] Navi 10 XL Upstream Port of PCI Express Switch [1002:1478] (rev c0)
02:00.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD/ATI] Navi 10 XL Downstream Port of PCI Express Switch [1002:1479]
03:00.0 VGA compatible controller [0300]: Advanced Micro Devices, Inc. [AMD/ATI] Navi 21 [Radeon RX 6800/6800 XT / 6900 XT] [1002:73bf] (rev c0)
03:00.1 Audio device [0403]: Advanced Micro Devices, Inc. [AMD/ATI] Navi 21/23 HDMI/DP Audio Controller [1002:ab28]
03:00.2 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD/ATI] Device [1002:73a6]
03:00.3 Serial bus controller [0c80]: Advanced Micro Devices, Inc. [AMD/ATI] Navi 21 USB [1002:73a4]
04:00.0 Non-Essential Instrumentation [1300]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Function [1022:148a]
05:00.0 Non-Essential Instrumentation [1300]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Reserved SPP [1022:1485]
05:00.3 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD] Starship USB 3.0 Host Controller [1022:148c]
20:00.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Root Complex [1022:1480]
20:00.2 IOMMU [0806]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse IOMMU [1022:1481]
20:01.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482]
20:02.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482]
20:03.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482]
20:04.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482]
20:05.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482]
20:07.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482]
20:07.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Internal PCIe GPP Bridge 0 to bus[E:B] [1022:1484]
20:08.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482]
20:08.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Internal PCIe GPP Bridge 0 to bus[E:B] [1022:1484]
21:00.0 Non-Essential Instrumentation [1300]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Function [1022:148a]
22:00.0 Non-Essential Instrumentation [1300]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Reserved SPP [1022:1485]
22:00.1 Encryption controller [1080]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Cryptographic Coprocessor PSPCPP [1022:1486]
22:00.3 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD] Starship USB 3.0 Host Controller [1022:148c]
22:00.4 Audio device [0403]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse HD Audio Controller [1022:1487]
40:00.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Root Complex [1022:1480]
40:00.2 IOMMU [0806]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse IOMMU [1022:1481]
40:01.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482]
40:01.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse GPP Bridge [1022:1483]
40:01.3 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse GPP Bridge [1022:1483]
40:02.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482]
40:03.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482]
40:04.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482]
40:05.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482]
40:07.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482]
40:07.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Internal PCIe GPP Bridge 0 to bus[E:B] [1022:1484]
40:08.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482]
40:08.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Internal PCIe GPP Bridge 0 to bus[E:B] [1022:1484]
41:00.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Matisse Switch Upstream [1022:57ad]
42:02.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Matisse PCIe GPP Bridge [1022:57a3]
42:03.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Matisse PCIe GPP Bridge [1022:57a3]
42:04.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Matisse PCIe GPP Bridge [1022:57a3]
42:05.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Matisse PCIe GPP Bridge [1022:57a3]
42:08.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Matisse PCIe GPP Bridge [1022:57a4]
42:09.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Matisse PCIe GPP Bridge [1022:57a4]
42:0a.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Matisse PCIe GPP Bridge [1022:57a4]
43:00.0 USB controller [0c03]: ASMedia Technology Inc. ASM3242 USB 3.2 Host Controller [1b21:3242]
44:00.0 Ethernet controller [0200]: Aquantia Corp. AQC107 NBase-T/IEEE 802.3bz Ethernet Controller [AQtion] [1d6a:07b1] (rev 02)
45:00.0 Network controller [0280]: Intel Corporation Wi-Fi 6 AX200 [8086:2723] (rev 1a)
46:00.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL8125 2.5GbE Controller [10ec:8125] (rev 01)
47:00.0 Non-Essential Instrumentation [1300]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Reserved SPP [1022:1485]
47:00.1 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD] Matisse USB 3.0 Host Controller [1022:149c]
47:00.3 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD] Matisse USB 3.0 Host Controller [1022:149c]
48:00.0 SATA controller [0106]: Advanced Micro Devices, Inc. [AMD] FCH SATA Controller [AHCI mode] [1022:7901] (rev 51)
49:00.0 SATA controller [0106]: Advanced Micro Devices, Inc. [AMD] FCH SATA Controller [AHCI mode] [1022:7901] (rev 51)
4a:00.0 Non-Volatile memory controller [0108]: Samsung Electronics Co Ltd NVMe SSD Controller PM9A1/PM9A3/980PRO [144d:a80a]
4b:00.0 Non-Essential Instrumentation [1300]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Function [1022:148a]
4c:00.0 Non-Essential Instrumentation [1300]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Reserved SPP [1022:1485]
60:00.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Root Complex [1022:1480]
60:00.2 IOMMU [0806]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse IOMMU [1022:1481]
60:01.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482]
60:02.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482]
60:03.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482]
60:04.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482]
60:05.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482]
60:07.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482]
60:07.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Internal PCIe GPP Bridge 0 to bus[E:B] [1022:1484]
60:08.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482]
60:08.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Internal PCIe GPP Bridge 0 to bus[E:B] [1022:1484]
61:00.0 Non-Essential Instrumentation [1300]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Function [1022:148a]
62:00.0 Non-Essential Instrumentation [1300]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Reserved SPP [1022:1485]Can you compile and run zencli to dump UMC
https://github.com/cyring/Tips/blob/master/C/zencli.c
cc zencli.c -o zencli
# run as root
zencli umcPlease post the output.
Chlorophytus
commented
2 years ago Data Fabric: scanning UMC @ BAR[0x00050000] : 0 1 2 3 4 5 6 7 for 4 Channels
CHA[0] CHIP[0:0] @ 0x00250000[0x00000000] Disable, Rank=0
CHA[0] MASK[0:0] @ 0x00250020[0x00000000]
CHA[0] CHIP[0:1] @ 0x00250010[0x00000000] Disable, Rank=0
CHA[0] MASK[0:1] @ 0x00250028[0x00000000]
CHA[0] CHIP[1:0] @ 0x00250004[0x00000000] Disable, Rank=0
CHA[0] MASK[1:0] @ 0x00250020[0x00000000]
CHA[0] CHIP[1:1] @ 0x00250014[0x00000000] Disable, Rank=0
CHA[0] MASK[1:1] @ 0x00250028[0x00000000]
CHA[0] CHIP[2:0] @ 0x00250008[0x00000001] Enable, Rank=2
CHA[0] MASK[2:0] @ 0x00250024[0x07fffdfe] ChipSize[16777216]
CHA[0] CHIP[2:1] @ 0x00250018[0x00000000] Disable, Rank=0
CHA[0] MASK[2:1] @ 0x0025002c[0x00000000]
CHA[0] CHIP[3:0] @ 0x0025000c[0x00000201] Enable, Rank=2
CHA[0] MASK[3:0] @ 0x00250024[0x07fffdfe] ChipSize[16777216]
CHA[0] CHIP[3:1] @ 0x00250018[0x00000000] Disable, Rank=0
CHA[0] MASK[3:1] @ 0x0025002c[0x00000000]
DIMM Size[33554432 KB] [32768 MB]
CHA[1] CHIP[0:0] @ 0x00350000[0x00000000] Disable, Rank=0
CHA[1] MASK[0:0] @ 0x00350020[0x00000000]
CHA[1] CHIP[0:1] @ 0x00350010[0x00000000] Disable, Rank=0
CHA[1] MASK[0:1] @ 0x00350028[0x00000000]
CHA[1] CHIP[1:0] @ 0x00350004[0x00000000] Disable, Rank=0
CHA[1] MASK[1:0] @ 0x00350020[0x00000000]
CHA[1] CHIP[1:1] @ 0x00350014[0x00000000] Disable, Rank=0
CHA[1] MASK[1:1] @ 0x00350028[0x00000000]
CHA[1] CHIP[2:0] @ 0x00350008[0x00000001] Enable, Rank=2
CHA[1] MASK[2:0] @ 0x00350024[0x07fffdfe] ChipSize[16777216]
CHA[1] CHIP[2:1] @ 0x00350018[0x00000000] Disable, Rank=0
CHA[1] MASK[2:1] @ 0x0035002c[0x00000000]
CHA[1] CHIP[3:0] @ 0x0035000c[0x00000201] Enable, Rank=2
CHA[1] MASK[3:0] @ 0x00350024[0x07fffdfe] ChipSize[16777216]
CHA[1] CHIP[3:1] @ 0x00350018[0x00000000] Disable, Rank=0
CHA[1] MASK[3:1] @ 0x0035002c[0x00000000]
DIMM Size[33554432 KB] [32768 MB]
CHA[2] CHIP[0:0] @ 0x00450000[0x00000000] Disable, Rank=0
CHA[2] MASK[0:0] @ 0x00450020[0x00000000]
CHA[2] CHIP[0:1] @ 0x00450010[0x00000000] Disable, Rank=0
CHA[2] MASK[0:1] @ 0x00450028[0x00000000]
CHA[2] CHIP[1:0] @ 0x00450004[0x00000000] Disable, Rank=0
CHA[2] MASK[1:0] @ 0x00450020[0x00000000]
CHA[2] CHIP[1:1] @ 0x00450014[0x00000000] Disable, Rank=0
CHA[2] MASK[1:1] @ 0x00450028[0x00000000]
CHA[2] CHIP[2:0] @ 0x00450008[0x00000001] Enable, Rank=2
CHA[2] MASK[2:0] @ 0x00450024[0x07fffdfe] ChipSize[16777216]
CHA[2] CHIP[2:1] @ 0x00450018[0x00000000] Disable, Rank=0
CHA[2] MASK[2:1] @ 0x0045002c[0x00000000]
CHA[2] CHIP[3:0] @ 0x0045000c[0x00000201] Enable, Rank=2
CHA[2] MASK[3:0] @ 0x00450024[0x07fffdfe] ChipSize[16777216]
CHA[2] CHIP[3:1] @ 0x00450018[0x00000000] Disable, Rank=0
CHA[2] MASK[3:1] @ 0x0045002c[0x00000000]
DIMM Size[33554432 KB] [32768 MB]
CHA[3] CHIP[0:0] @ 0x00550000[0x00000000] Disable, Rank=0
CHA[3] MASK[0:0] @ 0x00550020[0x00000000]
CHA[3] CHIP[0:1] @ 0x00550010[0x00000000] Disable, Rank=0
CHA[3] MASK[0:1] @ 0x00550028[0x00000000]
CHA[3] CHIP[1:0] @ 0x00550004[0x00000000] Disable, Rank=0
CHA[3] MASK[1:0] @ 0x00550020[0x00000000]
CHA[3] CHIP[1:1] @ 0x00550014[0x00000000] Disable, Rank=0
CHA[3] MASK[1:1] @ 0x00550028[0x00000000]
CHA[3] CHIP[2:0] @ 0x00550008[0x00000001] Enable, Rank=2
CHA[3] MASK[2:0] @ 0x00550024[0x07fffdfe] ChipSize[16777216]
CHA[3] CHIP[2:1] @ 0x00550018[0x00000000] Disable, Rank=0
CHA[3] MASK[2:1] @ 0x0055002c[0x00000000]
CHA[3] CHIP[3:0] @ 0x0055000c[0x00000201] Enable, Rank=2
CHA[3] MASK[3:0] @ 0x00550024[0x07fffdfe] ChipSize[16777216]
CHA[3] CHIP[3:1] @ 0x00550018[0x00000000] Disable, Rank=0
CHA[3] MASK[3:1] @ 0x0055002c[0x00000000]
DIMM Size[33554432 KB] [32768 MB]
Do you have 4 DIMMs, 32GB each ?
Chlorophytus
commented
2 years ago Do you have 4 DIMMs, 32GB each ?
Yes
cyring
commented
2 years ago Chlorophytus
commented
2 years ago Hello,
Can you try this attached version ?
That fixes it partially. Channels 0 and 1 are not detected.
cyring
commented
2 years ago Hello,
Can you test this one:
EDIT: you can also print all MC data with corefreq-cli -M
Chlorophytus
commented
2 years ago Thanks, that fixed it.
cyring
commented
2 years ago Thanks, that fixed it.
Great, can you please show me the output of corefreq-cli -M
Chlorophytus
commented
2 years ago Thanks, that fixed it.
Great, can you please show me the output of
corefreq-cli -M
accelshark@Funbox ~/Downloads/CoreFreq % ./corefreq-cli -M
Zen UMC [1490]
Controller #0 Quad Channel
Bus Rate 1800 MHz Bus Speed 1799 MHz DDR4 Speed 3599 MT/s
Cha CL RCDr RCDw RP RAS RC RRDs RRDl FAW WTRs WTRl WR clRR clWW
#0 18 22 22 22 42 82 6 9 38 5 14 26 5 5
#1 18 22 22 22 42 82 6 9 38 5 14 26 5 5
#2 18 22 22 22 42 82 6 9 38 5 14 26 5 5
#3 18 22 22 22 42 82 6 9 38 5 14 26 5 5
CWL RTP RdWr WrRd scWW sdWW ddWW scRR sdRR ddRR drRR drWW drWR drRRD
#0 18 14 7 3 1 7 6 1 5 4 0 0 0 0
#1 18 14 8 3 1 7 6 1 5 4 0 0 0 0
#2 18 14 7 3 1 7 6 1 5 4 0 0 0 0
#3 18 14 8 3 1 7 6 1 5 4 0 0 0 0
REFI RFC1 RFC2 RFC4 RCPB RPPB BGS:Alt Ban Page CKE CMD GDM ECC
#0 14029 312 192 132 0 0 OFF ON R1W1 0 0 1T ON 0
#1 14029 312 192 132 0 0 OFF ON R1W1 0 0 1T ON 0
#2 14029 312 192 132 0 0 OFF ON R1W1 0 0 1T ON 0
#3 14029 312 192 132 0 0 OFF ON R1W1 0 0 1T ON 0
MRD:PDA MOD:PDA WRMPR STAG PDM RDDATA WRD WRL RDL XS XP CPDED
#0 8 18 27 27 24 255 0:F:0 13 2 13 26 1008 11 4
#1 8 18 27 27 24 255 0:F:0 13 2 13 26 1008 11 4
#2 8 18 27 27 24 255 0:F:0 13 2 13 26 1008 11 4
#3 8 18 27 27 24 255 0:F:0 13 2 13 26 1008 11 4
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 16 2 131072 1024 32768
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 16 2 131072 1024 32768
DIMM Geometry for channel #2
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 16 2 131072 1024 32768
DIMM Geometry for channel #3
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 16 2 131072 1024 32768 This seems correct to me, the motherboard has 8 DIMM slots and only 4 are occupied.
I tried both the git and the regular AUR packages but the memory topology is not shown.
Using ASRock TRX40 Creator with beta BIOS 1.83. I have quad channel memory configuration, it should show 3600MHz on all 4 DIMMs.
The CastlePeakPI AGESA is 1.0.0.7