Closed N0tACyb0rg closed 1 year ago
I don't see other DID to query than 0x31f0
.
Shadow register does not help either; I wonder if other software are able to list the memory controller ?
Are you getting something from memtestx86
or CPUZ, OCCT, HWINFO ?
Here is an output from dmidecode
# dmidecode 3.4
Getting SMBIOS data from sysfs.
SMBIOS 3.1.1 present.
Handle 0x0025, DMI type 16, 23 bytes
Physical Memory Array
Location: System Board Or Motherboard
Use: System Memory
Error Correction Type: None
Maximum Capacity: 8 GB
Error Information Handle: Not Provided
Number Of Devices: 2
Handle 0x0027, DMI type 17, 40 bytes
Memory Device
Array Handle: 0x0025
Error Information Handle: Not Provided
Total Width: 16 bits
Data Width: 16 bits
Size: 8 GB
Form Factor: DIMM
Set: None
Locator: A1_DIMM0
Bank Locator: A1_BANK0
Type: DDR4
Type Detail: Synchronous
Speed: 2400 MT/s
Manufacturer: Hynix
Serial Number: 0000
Asset Tag: 9876543210
Part Number: 0000000000-00000
Rank: Unknown
Configured Memory Speed: 2400 MT/s
Minimum Voltage: 44.975 V
Maximum Voltage: 44.975 V
Configured Voltage: 1.5 V
Handle 0x0029, DMI type 17, 40 bytes
Memory Device
Array Handle: 0x0025
Error Information Handle: Not Provided
Total Width: Unknown
Data Width: 64 bits
Size: No Module Installed
Form Factor: DIMM
Set: None
Locator: A1_DIMM1
Bank Locator: A1_BANK1
Type: DDR2
Type Detail: Synchronous
Here is another output from the command lshw -short -C memory
:
H/W path Device Class Description
=================================================
/0/0 memory 64KiB BIOS
/0/25 memory 8GiB System Memory
/0/25/0 memory 8GiB DIMM DDR4 Synchronous 2400 MHz (0.4 ns)
/0/25/1 memory DIMM DDR2 Synchronous [empty]
/0/3f memory 224KiB L1 cache
/0/40 memory 4MiB L2 cache
Thanks but dmidecode, lshw are instrumentations based: SMBIOS, DMI, SPD for their lowest access level.
CoreFreq is Registers based; directly to the Memory Controller registers.
Memtest86+ is also one of the few Linux software which decodes IMC
https://github.com/memtest86plus/memtest86plus
If you are successfully reading the primary timings from Memtest86+ then MCHBAR
or another IMC protocol is feasible for CoreFreq
Memtest86+ is bootable, please take a photo if possible.
Hello,
In addition to Memtest86+, could you check if there is no BIOS option which locks the PCI MCH from being accessed ?
MCHBAR moved to #395
System Info:
I compiled from the develop branch with the provided make command for Intel systems:
make MSR_CORE_PERF_UC=MSR_CORE_PERF_FIXED_CTR1 MSR_CORE_PERF_URC=MSR_CORE_PERF_FIXED_CTR2
. I then attempted to insertcorefreqk.ko
usingsudo insmod corefreqk.ko
and got a kernel panic. I tried testing it by inserting it using the suggestion in #227,sudo insmod corefreqk.ko ArchID=11
and got a segmentation fault instead of a kernel panic. Here's the log for that from dmesg: pastebin.