Celeron(R) CPU N3150

[antermin]

Using 1e405b4:

$ corefreq-cli -s -n -m -n -B -n -M -n -C 1
Processor                              [Intel(R) Celeron(R) CPU N3150 @ 1.60GHz]
|- Architecture                                               [Airmont/Braswell]
|- Vendor ID                                                      [GenuineIntel]
|- Microcode                                                        [0x00000368]
|- Signature                                                           [  06_4C]
|- Stepping                                                            [      3]
|- Online CPU                                                          [  4/  4]
|- Base Clock                                                          [ 80.000]
|- Frequency            (MHz)                      Ratio                        
                 Min    480.00                    <   6 >                       
                 Max   1599.98                    <  20 >                       
|- Factory                                                             [ 80.000]
                       1600                       [  20 ]                       
|- Performance                                                                  
   |- P-State                                                                   
                 TGT    480.00                    <   6 >                       
|- Turbo Boost                                                         [ UNLOCK]
                  1C   2079.98                    <  26 >                       
                  2C   2079.98                    <  26 >                       
                  3C   2079.98                    <  26 >                       
                  4C   2079.98                    <  26 >                       
|- Uncore                                                              [   LOCK]
|- TDP                                                           Level [  0:0  ]
   |- Programmable                                                     [   LOCK]
   |- Configuration                                                    [   LOCK]
   |- Turbo Activation                                                 [   LOCK]
               Turbo   2079.98                    [  26 ]                       

Instruction Set Extensions                                                      
|- 3DNow!/Ext [N/N]          ADX [N]          AES [Y]  AVX/AVX2 [N/N] 
|- AVX512-F     [N]    AVX512-DQ [N]  AVX512-IFMA [N]   AVX512-PF [N] 
|- AVX512-ER    [N]    AVX512-CD [N]    AVX512-BW [N]   AVX512-VL [N] 
|- AVX512-VBMI  [N] AVX512-VBMI2 [N]  AVX512-VNNI [N]  AVX512-ALG [N] 
|- AVX512-VPOP  [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N] 
|- AVX512-BF16  [N] AVX-VNNI-VEX [N]      MOVDIRI [N]   MOVDIR64B [N] 
|- BMI1/BMI2  [N/N]         CLWB [N]      CLFLUSH [Y] CLFLUSH-OPT [N] 
|- CLAC-STAC    [N]         CMOV [Y]    CMPXCHG8B [Y]  CMPXCHG16B [Y] 
|- F16C         [N]          FPU [Y]         FXSR [Y]   LAHF-SAHF [Y] 
|- ENQCMD       [N]         GFNI [N]        OSPKE [N]     WAITPKG [N] 
|- MMX/Ext    [Y/N] MON/MWAITX [Y/N]        MOVBE [Y]   PCLMULQDQ [Y] 
|- POPCNT       [Y]       RDRAND [Y]       RDSEED [N]      RDTSCP [Y] 
|- SEP          [Y]          SHA [N]          SSE [Y]        SSE2 [Y] 
|- SSE3         [Y]        SSSE3 [Y]  SSE4.1/4A [Y/N]      SSE4.2 [Y] 
|- SERIALIZE    [N]      SYSCALL [Y]        RDPID [N]         SGX [N] 
|- VAES         [N]   VPCLMULQDQ [N]   PREFETCH/W [Y]       LZCNT [N] 

Features                                                                        
|- 1 GB Pages Support                                      1GB-PAGES   [Missing]
|- Advanced Configuration & Power Interface                     ACPI   [Capable]
|- Advanced Programmable Interrupt Controller                   APIC   [Capable]
|- APIC Timer Invariance                                        ARAT   [Capable]
|- Core Multi-Processing                                  CMP Legacy   [Missing]
|- L1 Data Cache Context ID                                  CNXT-ID   [Missing]
|- Direct Cache Access                                           DCA   [Missing]
|- Debugging Extension                                            DE   [Capable]
|- Debug Store & Precise Event Based Sampling               DS, PEBS   [Capable]
|- CPL Qualified Debug Store                                  DS-CPL   [Capable]
|- 64-Bit Debug Store                                         DTES64   [Capable]
|- Fast Short REP CMPSB                                         FSRC   [Missing]
|- Fast Short REP MOVSB                                         FSRM   [Missing]
|- Fast Short REP STOSB                                         FSRS   [Missing]
|- Fast Zero-length REP MOVSB                                   FZRM   [Missing]
|- Fast-String Operation                                        ERMS   [Capable]
|- Fused Multiply Add                                     FMA | FMA4   [Missing]
|- Hardware Feedback Interface                                   HFI   [Missing]
|- Hardware Lock Elision                                         HLE   [Missing]
|- History Reset                                              HRESET   [Missing]
|- Hybrid part processor                                      HYBRID   [Missing]
|- Instruction Based Sampling                                    IBS   [Missing]
|- Instruction INVPCID                                       INVPCID   [Missing]
|- Long Mode 64 bits                                       IA64 | LM   [Capable]
|- Linear Address Masking                                        LAM   [Missing]
|- LightWeight Profiling                                         LWP   [Missing]
|- Machine-Check Architecture                                    MCA   [Capable]
|- Memory Protection Extensions                                  MPX   [Missing]
|- Model Specific Registers                                      MSR   [Capable]
|- Memory Type Range Registers                                  MTRR   [Capable]
|- OS-Enabled Ext. State Management                          OSXSAVE   [Missing]
|- Physical Address Extension                                    PAE   [Capable]
|- Page Attribute Table                                          PAT   [Capable]
|- Pending Break Enable                                          PBE   [Capable]
|- Platform Configuration                                    PCONFIG   [Missing]
|- Process Context Identifiers                                  PCID   [Missing]
|- Perfmon and Debug Capability                                 PDCM   [Capable]
|- Page Global Enable                                            PGE   [Capable]
|- Page Size Extension                                           PSE   [Capable]
|- 36-bit Page Size Extension                                  PSE36   [Capable]
|- Processor Serial Number                                       PSN   [Missing]
|- Write Data to a Processor Trace Packet                    PTWRITE   [Missing]
|- Resource Director Technology/PQE                            RDT-A   [Missing]
|- Resource Director Technology/PQM                            RDT-M   [Missing]
|- Restricted Transactional Memory                               RTM   [Missing]
|- Safer Mode Extensions                                         SMX   [Missing]
|- Self-Snoop                                                     SS   [Capable]
|- Supervisor-Mode Access Prevention                            SMAP   [Missing]
|- Supervisor-Mode Execution Prevention                         SMEP   [Capable]
|- Thread Director                                                TD   [Missing]
|- Time Stamp Counter                                            TSC [Invariant]
|- Time Stamp Counter Deadline                          TSC-DEADLINE   [Capable]
|- TSX Force Abort MSR Register                            TSX-ABORT   [Missing]
|- TSX Suspend Load Address Tracking                       TSX-LDTRK   [Missing]
|- User-Mode Instruction Prevention                             UMIP   [Missing]
|- Virtual Mode Extension                                        VME   [Capable]
|- Virtual Machine Extensions                                    VMX   [Capable]
|- Write Back & Do Not Invalidate Cache                     WBNOINVD   [Missing]
|- Extended xAPIC Support                                     x2APIC   [Missing]
|- Execution Disable Bit Support                              XD-Bit   [Capable]
|- XSAVE/XSTOR States                                          XSAVE   [Missing]
|- xTPR Update Control                                          xTPR   [Capable]
Mitigation mechanisms                                                           
|- Indirect Branch Restricted Speculation                       IBRS   [Capable]
|- Indirect Branch Prediction Barrier                           IBPB   [Capable]
|- Single Thread Indirect Branch Predictor                     STIBP   [Capable]
|- Speculative Store Bypass Disable                             SSBD   [ Unable]
|- Writeback & invalidate the L1 data cache                L1D-FLUSH   [ Unable]
|- Hypervisor - No flush L1D on VM entry            L1DFL_VMENTRY_NO   [ Unable]
|- Arch - Buffer Overwriting                                MD-CLEAR   [Capable]
|- Arch - No Rogue Data Cache Load                           RDCL_NO   [ Unable]
|- Arch - Enhanced IBRS                                     IBRS_ALL   [ Unable]
|- Arch - Return Stack Buffer Alternate                         RSBA   [ Unable]
|- Arch - No Speculative Store Bypass                         SSB_NO   [ Unable]
|- Arch - No Microarchitectural Data Sampling                 MDS_NO   [ Unable]
|- Arch - No TSX Asynchronous Abort                           TAA_NO   [ Unable]
|- Arch - No Page Size Change MCE                     PSCHANGE_MC_NO   [ Unable]
|- Arch - STLB QoS                                              STLB   [ Unable]
|- Arch - Functional Safety Island                              FuSa   [ Unable]
|- Arch - RSM in CPL0 only                                       RSM   [ Unable]
|- Arch - Split Locked Access Exception                         SPLA   [ Unable]
|- Arch - Snoop Filter QoS Mask                         SNOOP_FILTER   [ Unable]
|- Arch - No Fast Predictive Store Forwarding                   PSFD   [ Unable]
|- Arch - Data Operand Independent Timing Mode                 DOITM   [ Unable]
|- Arch - Not affected by SBDR or SSDP                  SBDR_SSDP_NO   [ Unable]
|- Arch - No Fill Buffer Stale Data Propagator              FBSDP_NO   [ Unable]
|- Arch - No Primary Stale Data Propagator                   PSDP_NO   [ Unable]
|- Arch - Overwrite Fill Buffer values                      FB_CLEAR   [ Unable]
|- Arch - Special Register Buffer Data Sampling                SRBDS   [ Unable]
   |- RDRAND and RDSEED mitigation                             RNGDS   [ Unable]
   |- Restricted Transactional Memory                            RTM   [ Unable]
   |- Verify Segment for Writing instruction                    VERW   [ Unable]
|- Arch - Restricted RSB Alternate                             RRSBA   [ Unable]
|- Arch - No Branch Target Injection                          BHI_NO   [ Unable]
|- Arch - Legacy xAPIC Disable                             XAPIC_DIS   [ Unable]
|- Arch - No Post-Barrier Return Stack Buffer               PBRSB_NO   [ Unable]
|- Arch - IPRED disabled for CPL3                        IPRED_DIS_U   [ Unable]
|- Arch - IPRED disabled for CPL0/1/2                    IPRED_DIS_S   [ Unable]
|- Arch - RRSBA disabled for CPL3                        RRSBA_DIS_U   [ Unable]
|- Arch - RRSBA disabled for CPL0/1/2                    RRSBA_DIS_S   [ Unable]
|- Arch - BHI disabled for CPL0/1/2                        BHI_DIS_S   [ Unable]
|- No MXCSR Configuration Dependent Timing                   MCDT_NO   [ Unable]
Security Features                                                               
|- CPUID Key Locker                                               KL   [Missing]
|- AES Key Locker instructions                                AESKLE   [Capable]
|- AES Wide Key Locker instructions                          WIDE_KL   [Missing]
|- Software Guard SGX1 Extensions                               SGX1   [Capable]
|- Software Guard SGX2 Extensions                               SGX2   [Missing]

Technologies                                                                    
|- Data Cache Unit                                                              
   |- L1 Prefetcher                                                L1 HW   < ON>
   |- L1 IP Prefetcher                                          L1 HW IP   < ON>
   |- L2 Prefetcher                                                L2 HW   < ON>
   |- L2 Line Prefetcher                                        L2 HW CL   < ON>
|- System Management Mode                                       SMM-Dual   [OFF]
|- Hyper-Threading                                                   HTT   [OFF]
|- SpeedStep                                                        EIST   < ON>
|- Dynamic Acceleration                                              IDA   [ ON]
|- Turbo Boost                                                     TURBO   < ON>
|- Energy Efficiency Optimization                                    EEO   <OFF>
|- Race To Halt Optimization                                         R2H   <OFF>
|- Watchdog Timer                                                    TCO   <OFF>
|- Virtualization                                                    VMX   [ ON]
   |- I/O MMU                                                       VT-d   [OFF]
   |- Version                                                     [         N/A]
   |- Hypervisor                                                           [OFF]
   |- Vendor ID                                                   [         N/A]

Performance Monitoring                                                          
|- Version                                                        PM       [  3]
|- Counters:          General                   Fixed                           
|           {  2,  0,  0 } x 40 bits            3 x 40 bits                     
|- Enhanced Halt State                                           C1E       <OFF>
|- C1 Auto Demotion                                              C1A       <OFF>
|- C3 Auto Demotion                                              C3A       <OFF>
|- C1 UnDemotion                                                 C1U       <OFF>
|- C3 UnDemotion                                                 C3U       <OFF>
|- C6 Core Demotion                                              CC6       <OFF>
|- C6 Module Demotion                                            MC6       <OFF>
|- Legacy Frequency ID control                                   FID       [OFF]
|- Legacy Voltage ID control                                     VID       [OFF]
|- P-State Hardware Coordination Feedback                MPERF/APERF       [ ON]
|- Hardware Duty Cycling                                         HDC       [OFF]
|- Package C-States                                                             
   |- Configuration Control                                   CONFIG   [ UNLOCK]
   |- Lowest C-State                                           LIMIT   <     C1>
   |- I/O MWAIT Redirection                                  IOMWAIT   <Disable>
   |- Max C-State Inclusion                                    RANGE   <     C3>
|- Core C-States                                                                
   |- C-States Base Address                                      BAR   [ 0x0   ]
|- ACPI Processor C-States                                      _CST   [Missing]
|- MONITOR/MWAIT                                                                
   |- State index:    #0    #1    #2    #3    #4    #5    #6    #7              
   |- Sub C-State:     0     2     0     0     0     0     3     3              
|- Core Cycles                                                         [Capable]
|- Instructions Retired                                                [Capable]
|- Reference Cycles                                                    [Capable]
|- Last Level Cache References                                         [Capable]
|- Last Level Cache Misses                                             [Capable]
|- Branch Instructions Retired                                         [Capable]
|- Branch Mispredicts Retired                                          [Capable]
|- Top-down slots Counter                                              [Capable]
|- Processor Performance Control                                _PCT   [Missing]
|- Performance Supported States                                 _PSS   [Missing]
|- Performance Present Capabilities                             _PPC   [Missing]

Power, Current & Thermal                                                        
|- Temperature Offset:Junction                                 TjMax <  0: 90 C>
|- Clock Modulation                                             ODCM   <Disable>
   |- DutyCycle                                                        [  0.00%]
|- Power Management                                         PWR MGMT   [   LOCK]
   |- Energy Policy                                        Bias Hint   <      0>
|- Digital Thermal Sensor                                        DTS   [Capable]
|- Power Limit Notification                                      PLN   [Missing]
|- Package Thermal Management                                    PTM   [Missing]
|- Thermal Monitor 1                                             TM1   [Capable]
|- Thermal Monitor 2                                             TM2   [Capable]
|- Thermal Design Power                                          TDP   [Missing]
   |- Minimum Power                                              Min   [Missing]
   |- Maximum Power                                              Max   [Missing]
|- Thermal Design Power                                      Package   < Enable>
   |- Power Limit                                                PL1   <   14 W>
   |- Time Window                                                TW1   < 3.03 d>
   |- Power Limit                                                PL2   <   14 W>
   |- Time Window                                                TW2   <    1 s>
|- Thermal Design Power                                         Core   <Disable>
   |- Power Limit                                                PL1   <    0 W>
   |- Time Window                                                TW1   < 976 us>
|- Thermal Design Power                                       Uncore   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [ 976 us]
|- Thermal Design Power                                         DRAM   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [ 976 us]
|- Thermal Design Power                                     Platform   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [ 976 us]
   |- Power Limit                                                PL2   [    0 W]
   |- Time Window                                                TW2   [ 976 us]
|- Electrical Design Current                                     EDC   [Missing]
|- Thermal Design Current                                        TDC   [Missing]
|- Core Thermal Point                                                           
   |- DTS Threshold #1                                     Threshold   [Missing]
   |- DTS Threshold #2                                     Threshold   [Missing]
|- Package Thermal Point                                                        
|- Units                                                                        
   |- Power                                               watt   [  0.000031250]
   |- Energy                                             joule   [  0.000031250]
   |- Window                                            second   [  0.000976562]

CPU Pkg  Apic  Core/Thread  Caches      (w)rite-Back (i)nclusive              
 #   ID   ID    ID     ID  L1-Inst Way  L1-Data Way      L2  Way      L3  Way 
000:BSP    0     0      0    32768  8w    24576  6w  1048576 16w        0  0  
001:  0    2     1      0    32768  8w    24576  6w  1048576 16w        0  0  
002:  0    4     2      0    32768  8w    24576  6w  1048576 16w        0  0  
003:  0    6     3      0    32768  8w    24576  6w  1048576 16w        0  0  

[ 0] American Megatrends Inc.                                                   
[ 1] P1.70                                                                      
[ 2] 02/27/2018                                                                 
[ 3] To Be Filled By O.E.M.                                                     
[ 4] To Be Filled By O.E.M.                                                     
[ 5] To Be Filled By O.E.M.                                                     
[ 6] 6---X---0---                                                               
[ 7] To Be Filled By O.E.M.                                                     
[ 8] To Be Filled By O.E.M.                                                     
[ 9] ASRock                                                                     
[10] N3150-NUC                                                                  
[11]                                                                            
[12] 1---2---0---1--                                                            
[13] Number Of Devices:2\Maximum Capacity:8388608 bytes                         
[14] A1_DIMM0\A1_BANK0                                                          
[15] A1_DIMM1\A1_BANK1                                                          
[16]                                                                            
[17]                                                                            
[18] Micron                                                                     
[19] Micron                                                                     
[20]                                                                            
[21]                                                                            
[22] A1_AssetTagNum0                                                            
[23] A1_AssetTagNum1                                                            
[24]                                                                            
[25]                                                                            

                              Airmont  [2280]                              
Controller #0                                                Dual Channel  
 Bus Rate  5000 MT/s      Bus Speed 4999 MT/s          DDR3 Speed  800 MHz 

 Cha    CL  RCD   RP  RAS  RRD  RFC   WR RTPr WTPr  FAW  B2B  CWL CMD  REFI
  #0     9   11    8   12    5  256    0   10   24   24    0    8  2T  1560
  #1     9   11    8   12    5  256    0   10   24   24    0    8  2T  1560
      ddWR drWR srWR ddRW drRW srRW ddRR drRR srRR ddWW drWW srWW CKE   ECC
  #0     4    6   19   10    7    8    0   10    0    4    6    0   0    1 
  #1     4    6   19   10    7    8    0   10    0    4    6    0   0    1 

 DIMM Geometry for channel #0                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0     8    2     65536      1024           8192     A1_AssetTagNum0
 DIMM Geometry for channel #1                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0                                                                  

CPU Freq(MHz) VID  Vcore  TMP(C)    Accumulator       Energy(J)     Power(W)
000   18.03    45  0.4700   46  000000000000000000    0.000000000   0.000000000
001    2.80    45  0.4700   46  000000000000000000    0.000000000   0.000000000
002   11.13    45  0.4700   43  000000000000000000    0.000000000   0.000000000
003    4.05    45  0.4700   43  000000000000000000    0.000000000   0.000000000

             Package[0]    Cores         Uncore        Memory        Platform
Energy(J):   0.726062500   0.074750000   0.000000000   0.000000000   0.000000000
Power(W) :   0.726062500   0.074750000   0.000000000   0.000000000   0.000000000

[antermin]

One thing I noticed is that the memory information seems bugged:

• I have 2x 16KTF1G64HZ-1G6E1 installed, but:
  • Instead of showing the part number, it shows "A1_AssetTagNum0".
  • It also only shows 1 module and the information for another module (channel 1) is missing.
• It says Bus Rate 5000 MT/s Bus Speed 4999 MT/s but:
  • N3150 supports DDR3-1600
  • i7-7567U supports DDR4-2133 (#400 Bus Rate 4000 MT/s Bus Speed 4004 MT/s, there is no way that 7567U is performs worse than N3150)

[cyring]

Yes, Braswell IMC is definitely a work in progress. I used to have Contributors. Since, no answer. I'm glade you came here to help.

I've to prepare another CoreFreq source archive to let you test all Braswell specifics. Won't be long.

[cyring]

Now that develop can be loaded, would you refresh the CLI output to check first about the architecture name ?

[antermin]

Now that develop can be loaded, would you refresh the CLI output to check first about the architecture name ?

The first comment has been edited to the refreshed CLI output, it is now showing Airmont/Braswell.

[cyring]

Now that develop can be loaded, would you refresh the CLI output to check first about the architecture name ?

The first comment has been edited to the refreshed CLI output, it is now showing Airmont/Braswell.

Looks better, thanks.

I can't tell why A1_AssetTagNum0is encoded into SMBIOS rather than 16KTF1G64HZ-1G6E1 but true the second stick is missing.

Edit: Aren't those two 800 MHz aka 1600 MT/s DDR3 DIMMs ?

Bus needs indeed more work; to find a setting register rather than default DMI link.

[antermin]

For reference:

# dmidecode -t 17
# dmidecode 3.4
Getting SMBIOS data from sysfs.
SMBIOS 2.8 present.

Handle 0x000C, DMI type 17, 40 bytes
Memory Device
        Array Handle: 0x000A
        Error Information Handle: Not Provided
        Total Width: 64 bits
        Data Width: 64 bits
        Size: 8 GB
        Form Factor: DIMM
        Set: None
        Locator: A1_DIMM0
        Bank Locator: A1_BANK0
        Type: DDR3
        Type Detail: Unknown
        Speed: 1600 MT/s
        Manufacturer: Micron          
        Serial Number: 0CBC140F  
        Asset Tag: A1_AssetTagNum0
        Part Number: 16KTF1G64HZ-1G6E1 
        Rank: 2
        Configured Memory Speed: 1600 MT/s
        Minimum Voltage: 1.35 V
        Maximum Voltage: 1.5 V
        Configured Voltage: 1.35 V

Handle 0x000E, DMI type 17, 40 bytes
Memory Device
        Array Handle: 0x000A
        Error Information Handle: Not Provided
        Total Width: 64 bits
        Data Width: 64 bits
        Size: 8 GB
        Form Factor: DIMM
        Set: None
        Locator: A1_DIMM1
        Bank Locator: A1_BANK1
        Type: DDR3
        Type Detail: Unknown
        Speed: 1600 MT/s
        Manufacturer: Micron          
        Serial Number: 0D9A066B  
        Asset Tag: A1_AssetTagNum1
        Part Number: 16KTF1G64HZ-1G6E1 
        Rank: 2
        Configured Memory Speed: 1600 MT/s
        Minimum Voltage: 1.35 V
        Maximum Voltage: 1.5 V
        Configured Voltage: 1.35 V

[cyring]

Thanks. 1600 MT/s is confirmed. A1_AssetTagNum appears like a buggy BIOS. Nothing I can do from those SMBIOS fields.

[cyring]

Thanks. 1600 MT/s is confirmed. A1_AssetTagNum appears like a buggy BIOS. Nothing I can do from those SMBIOS fields.

@antermin

DMI_ENTRY_MEM_DEVICE seems to de-synchronize past manufacturer_id field https://github.com/cyring/CoreFreq/blob/07ea6d41153852866ccb6d6287abc9b6ed699b73/corefreqk.h#L1370

I'm comparing my SMBIOS_Entries parser with dmidecode.c code but don't find a SMBIOS exception, neither in latest DMTF specification DSP0134_3.6.0.pdf

[cyring]

One thing I noticed is that the memory information seems bugged:

• I have 2x 16KTF1G64HZ-1G6E1 installed, but:

  • Instead of showing the part number, it shows "A1_AssetTagNum0".
  • It also only shows 1 module and the information for another module (channel 1) is missing.

I'm finding my mistake among the Registers addresses I should decode the Airmont IMC from. Using the Silvermont registers appears to provide some Timings but I have been lucky and I have no guarantee Timings are those you are reading in BIOS ?

I now have to program a dedicated Airmont IMC decoder and I need to know if your processor is still available for testing code ?

---

Meanwhile, I don't find the datasheet volume 2

• 332095 Specification Update
• 332093 Volume 2 provides the Registers specification I need.

EDIT but Airmont is supposed to be a die shrink of Silvermont. Does it mean I can apply the same IMC decoder ? The decoder programmed for Silvermont/Celeron N2930

[antermin]

Yes, I still have the processor for testing.

[cyring]

Yes, I still have the processor for testing.

Great, thank you. Could you tell me if tbe found timings are correct ?

[antermin]

The BIOS shows no timings information, so I used mt86plus_6.01_64.iso.zip and it shows 11-11-11-28.

[cyring]

The BIOS shows no timings information, so I used mt86plus_6.01_64.iso.zip and it shows 11-11-11-28.

According to its source code, it seems to show SPD but not the configured IMC by BIOS. Looking specs of 16KTF1G64HZ-1G6E1, I'm finding CL11. CoreFreq has decoded CL9 and remaining timings look coherent with DDR3, I still don't know which one is true ?

[antermin]

Not sure whether the following is useful, but anyway, this is what I get for another PC (unknown brand) with N3050:

corefreq 1.95.1

``` $ corefreq-cli -s -n -m -n -B -n -M -n -C 1 Processor [Intel(R) Celeron(R) CPU N3050 @ 1.60GHz] |- Architecture [Airmont/Braswell] |- Vendor ID [GenuineIntel] |- Microcode [0x00000362] |- Signature [ 06_4C] |- Stepping [ 3] |- Online CPU [ 2/ 2] |- Base Clock [ 79.997] |- Frequency (MHz) Ratio Min 479.98 < 6 > Max 1599.94 < 20 > |- Factory [ 80.000] 1600 [ 20 ] |- Performance |- P-State TGT 479.98 < 6 > |- Turbo Boost [ UNLOCK] 1C 2159.92 < 27 > 2C 2159.92 < 27 > |- Uncore [ LOCK] |- TDP Level [ 0:0 ] |- Programmable [ LOCK] |- Configuration [ LOCK] |- Turbo Activation [ LOCK] Turbo 2159.92 [ 27 ] Instruction Set Extensions |- 3DNow!/Ext [N/N] ADX [N] AES [Y] AVX/AVX2 [N/N] |- AVX512-F [N] AVX512-DQ [N] AVX512-IFMA [N] AVX512-PF [N] |- AVX512-ER [N] AVX512-CD [N] AVX512-BW [N] AVX512-VL [N] |- AVX512-VBMI [N] AVX512-VBMI2 [N] AVX512-VNNI [N] AVX512-ALG [N] |- AVX512-VPOP [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N] |- AVX512-BF16 [N] AVX-VNNI-VEX [N] MOVDIRI [N] MOVDIR64B [N] |- BMI1/BMI2 [N/N] CLWB [N] CLFLUSH [Y] CLFLUSH-OPT [N] |- CLAC-STAC [N] CMOV [Y] CMPXCHG8B [Y] CMPXCHG16B [Y] |- F16C [N] FPU [Y] FXSR [Y] LAHF-SAHF [Y] |- ENQCMD [N] GFNI [N] OSPKE [N] WAITPKG [N] |- MMX/Ext [Y/N] MON/MWAITX [Y/N] MOVBE [Y] PCLMULQDQ [Y] |- POPCNT [Y] RDRAND [Y] RDSEED [N] RDTSCP [Y] |- SEP [Y] SHA [N] SSE [Y] SSE2 [Y] |- SSE3 [Y] SSSE3 [Y] SSE4.1/4A [Y/N] SSE4.2 [Y] |- SERIALIZE [N] SYSCALL [Y] RDPID [N] SGX [N] |- VAES [N] VPCLMULQDQ [N] PREFETCH/W [Y] LZCNT [N] Features |- 1 GB Pages Support 1GB-PAGES [Missing] |- Advanced Configuration & Power Interface ACPI [Capable] |- Advanced Programmable Interrupt Controller APIC [Capable] |- APIC Timer Invariance ARAT [Capable] |- Core Multi-Processing CMP Legacy [Missing] |- L1 Data Cache Context ID CNXT-ID [Missing] |- Direct Cache Access DCA [Missing] |- Debugging Extension DE [Capable] |- Debug Store & Precise Event Based Sampling DS, PEBS [Capable] |- CPL Qualified Debug Store DS-CPL [Capable] |- 64-Bit Debug Store DTES64 [Capable] |- Fast Short REP CMPSB FSRC [Missing] |- Fast Short REP MOVSB FSRM [Missing] |- Fast Short REP STOSB FSRS [Missing] |- Fast Zero-length REP MOVSB FZRM [Missing] |- Fast-String Operation ERMS [Capable] |- Fused Multiply Add FMA | FMA4 [Missing] |- Hardware Feedback Interface HFI [Missing] |- Hardware Lock Elision HLE [Missing] |- History Reset HRESET [Missing] |- Hybrid part processor HYBRID [Missing] |- Instruction Based Sampling IBS [Missing] |- Instruction INVPCID INVPCID [Missing] |- Long Mode 64 bits IA64 | LM [Capable] |- Linear Address Masking LAM [Missing] |- LightWeight Profiling LWP [Missing] |- Machine-Check Architecture MCA [Capable] |- Memory Protection Extensions MPX [Missing] |- Model Specific Registers MSR [Capable] |- Memory Type Range Registers MTRR [Capable] |- OS-Enabled Ext. State Management OSXSAVE [Missing] |- Physical Address Extension PAE [Capable] |- Page Attribute Table PAT [Capable] |- Pending Break Enable PBE [Capable] |- Platform Configuration PCONFIG [Missing] |- Process Context Identifiers PCID [Missing] |- Perfmon and Debug Capability PDCM [Capable] |- Page Global Enable PGE [Capable] |- Page Size Extension PSE [Capable] |- 36-bit Page Size Extension PSE36 [Capable] |- Processor Serial Number PSN [Missing] |- Write Data to a Processor Trace Packet PTWRITE [Missing] |- Resource Director Technology/PQE RDT-A [Missing] |- Resource Director Technology/PQM RDT-M [Missing] |- Restricted Transactional Memory RTM [Missing] |- Safer Mode Extensions SMX [Missing] |- Self-Snoop SS [Capable] |- Supervisor-Mode Access Prevention SMAP [Missing] |- Supervisor-Mode Execution Prevention SMEP [Capable] |- Thread Director TD [Missing] |- Time Stamp Counter TSC [Invariant] |- Time Stamp Counter Deadline TSC-DEADLINE [Capable] |- TSX Force Abort MSR Register TSX-ABORT [Missing] |- TSX Suspend Load Address Tracking TSX-LDTRK [Missing] |- User-Mode Instruction Prevention UMIP [Missing] |- Virtual Mode Extension VME [Capable] |- Virtual Machine Extensions VMX [Capable] |- Write Back & Do Not Invalidate Cache WBNOINVD [Missing] |- Extended xAPIC Support x2APIC [Missing] |- Execution Disable Bit Support XD-Bit [Capable] |- XSAVE/XSTOR States XSAVE [Missing] |- xTPR Update Control xTPR [Capable] Mitigation mechanisms |- Indirect Branch Restricted Speculation IBRS [ Unable] |- Indirect Branch Prediction Barrier IBPB [ Unable] |- Single Thread Indirect Branch Predictor STIBP [ Unable] |- Speculative Store Bypass Disable SSBD [ Unable] |- Writeback & invalidate the L1 data cache L1D-FLUSH [ Unable] |- Hypervisor - No flush L1D on VM entry L1DFL_VMENTRY_NO [ Unable] |- Arch - Buffer Overwriting MD-CLEAR [ Unable] |- Arch - No Rogue Data Cache Load RDCL_NO [ Unable] |- Arch - Enhanced IBRS IBRS_ALL [ Unable] |- Arch - Return Stack Buffer Alternate RSBA [ Unable] |- Arch - No Speculative Store Bypass SSB_NO [ Unable] |- Arch - No Microarchitectural Data Sampling MDS_NO [ Unable] |- Arch - No TSX Asynchronous Abort TAA_NO [ Unable] |- Arch - No Page Size Change MCE PSCHANGE_MC_NO [ Unable] |- Arch - STLB QoS STLB [ Unable] |- Arch - Functional Safety Island FuSa [ Unable] |- Arch - RSM in CPL0 only RSM [ Unable] |- Arch - Split Locked Access Exception SPLA [ Unable] |- Arch - Snoop Filter QoS Mask SNOOP_FILTER [ Unable] |- Arch - No Fast Predictive Store Forwarding PSFD [ Unable] |- Arch - Data Operand Independent Timing Mode DOITM [ Unable] |- Arch - Not affected by SBDR or SSDP SBDR_SSDP_NO [ Unable] |- Arch - No Fill Buffer Stale Data Propagator FBSDP_NO [ Unable] |- Arch - No Primary Stale Data Propagator PSDP_NO [ Unable] |- Arch - Overwrite Fill Buffer values FB_CLEAR [ Unable] |- Arch - Special Register Buffer Data Sampling SRBDS [ Unable] |- RDRAND and RDSEED mitigation RNGDS [ Unable] |- Restricted Transactional Memory RTM [ Unable] |- Verify Segment for Writing instruction VERW [ Unable] |- Arch - Restricted RSB Alternate RRSBA [ Unable] |- Arch - No Branch Target Injection BHI_NO [ Unable] |- Arch - Legacy xAPIC Disable XAPIC_DIS [ Unable] |- Arch - No Post-Barrier Return Stack Buffer PBRSB_NO [ Unable] |- Arch - IPRED disabled for CPL3 IPRED_DIS_U [ Unable] |- Arch - IPRED disabled for CPL0/1/2 IPRED_DIS_S [ Unable] |- Arch - RRSBA disabled for CPL3 RRSBA_DIS_U [ Unable] |- Arch - RRSBA disabled for CPL0/1/2 RRSBA_DIS_S [ Unable] |- Arch - BHI disabled for CPL0/1/2 BHI_DIS_S [ Unable] |- No MXCSR Configuration Dependent Timing MCDT_NO [ Unable] Security Features |- CPUID Key Locker KL [Missing] |- AES Key Locker instructions AESKLE [Capable] |- AES Wide Key Locker instructions WIDE_KL [Missing] |- Software Guard SGX1 Extensions SGX1 [Capable] |- Software Guard SGX2 Extensions SGX2 [Missing] Technologies |- Data Cache Unit |- L1 Prefetcher L1 HW < ON> |- L1 IP Prefetcher L1 HW IP < ON> |- L2 Prefetcher L2 HW < ON> |- L2 Line Prefetcher L2 HW CL < ON> |- System Management Mode SMM-Dual [ ON] |- Hyper-Threading HTT [OFF] |- SpeedStep EIST < ON> |- Dynamic Acceleration IDA [ ON] |- Turbo Boost TURBO < ON> |- Energy Efficiency Optimization EEO |- Race To Halt Optimization R2H |- Watchdog Timer TCO |- Virtualization VMX [ ON] |- I/O MMU VT-d [OFF] |- Version [ N/A] |- Hypervisor [OFF] |- Vendor ID [ N/A] Performance Monitoring |- Version PM [ 3] |- Counters: General Fixed | { 2, 0, 0 } x 40 bits 3 x 40 bits |- Enhanced Halt State C1E |- C1 Auto Demotion C1A |- C3 Auto Demotion C3A |- C1 UnDemotion C1U |- C3 UnDemotion C3U |- C6 Core Demotion CC6 |- C6 Module Demotion MC6 |- Legacy Frequency ID control FID [OFF] |- Legacy Voltage ID control VID [OFF] |- P-State Hardware Coordination Feedback MPERF/APERF [ ON] |- Hardware Duty Cycling HDC [OFF] |- Package C-States |- Configuration Control CONFIG [ UNLOCK] |- Lowest C-State LIMIT < C7> |- I/O MWAIT Redirection IOMWAIT |- Max C-State Inclusion RANGE < C7> |- Core C-States |- C-States Base Address BAR [ 0x0 ] |- ACPI Processor C-States _CST [Missing] |- MONITOR/MWAIT |- State index: #0 #1 #2 #3 #4 #5 #6 #7 |- Sub C-State: 0 2 0 0 0 0 3 3 |- Core Cycles [Capable] |- Instructions Retired [Capable] |- Reference Cycles [Capable] |- Last Level Cache References [Capable] |- Last Level Cache Misses [Capable] |- Branch Instructions Retired [Capable] |- Branch Mispredicts Retired [Capable] |- Top-down slots Counter [Capable] |- Processor Performance Control _PCT [Missing] |- Performance Supported States _PSS [Missing] |- Performance Present Capabilities _PPC [Missing] Power, Current & Thermal |- Temperature Offset:Junction TjMax < 0: 90 C> |- Clock Modulation ODCM |- DutyCycle [ 0.00%] |- Power Management PWR MGMT [ LOCK] |- Energy Policy Bias Hint < 0> |- Digital Thermal Sensor DTS [Capable] |- Power Limit Notification PLN [Missing] |- Package Thermal Management PTM [Missing] |- Thermal Monitor 1 TM1 [ Enable] |- Thermal Monitor 2 TM2 [Capable] |- Thermal Design Power TDP [Missing] |- Minimum Power Min [Missing] |- Maximum Power Max [Missing] |- Thermal Design Power Package < Enable> |- Power Limit PL1 < 5 W> |- Time Window TW1 < 3.03 d> |- Power Limit PL2 < 14 W> |- Time Window TW2 < 1 s> |- Thermal Design Power Core |- Power Limit PL1 < 0 W> |- Time Window TW1 < 976 us> |- Thermal Design Power Uncore [Disable] |- Power Limit PL1 [ 0 W] |- Time Window TW1 [ 976 us] |- Thermal Design Power DRAM [Disable] |- Power Limit PL1 [ 0 W] |- Time Window TW1 [ 976 us] |- Thermal Design Power Platform [Disable] |- Power Limit PL1 [ 0 W] |- Time Window TW1 [ 976 us] |- Power Limit PL2 [ 0 W] |- Time Window TW2 [ 976 us] |- Electrical Design Current EDC [Missing] |- Thermal Design Current TDC [Missing] |- Core Thermal Point |- DTS Threshold #1 Threshold [Missing] |- DTS Threshold #2 Threshold [Missing] |- Package Thermal Point |- Units |- Power watt [ 0.000031250] |- Energy joule [ 0.000031250] |- Window second [ 0.000976562] CPU Pkg Apic Core/Thread Caches (w)rite-Back (i)nclusive # ID ID ID ID L1-Inst Way L1-Data Way L2 Way L3 Way 000:BSP 0 0 0 32768 8w 24576 6w 1048576 16w 0 0 001: 0 4 2 0 32768 8w 24576 6w 1048576 16w 0 0 [ 0] American Megatrends Inc. [ 1] 5.11 [ 2] 06/23/2016 [ 3] Default string [ 4] Default string [ 5] Default string [ 6] D---u---s---n- [ 7] Default string [ 8] Default string [ 9] AMI Corporation [10] Aptio CRB [11] Default string [12] D---u---s---n- [13] Number Of Devices:2\Maximum Capacity:8388608 kilobytes [14] A1_DIMM0\A1_BANK0 [15] [16] [17] [18] Samsung [19] [20] [21] [22] A1_AssetTagNum0 [23] [24] [25] Airmont [2280] Controller #0 Single Channel Bus Rate 5000 MT/s Bus Speed 4999 MT/s DDR3 Speed 800 MHz Cha CL RCD RP RAS RRD RFC WR RTPr WTPr FAW B2B CWL CMD REFI #0 9 11 8 12 5 256 0 10 24 24 0 8 2T 0 ddWR drWR srWR ddRW drRW srRW ddRR drRR srRR ddWW drWW srWW CKE ECC #0 4 7 19 10 7 8 0 10 0 4 6 0 0 0 DIMM Geometry for channel #0 Slot Bank Rank Rows Columns Memory Size (MB) #0 8 1 65536 1024 4096 A1_AssetTagNum0 CPU Freq(MHz) VID Vcore TMP(C) Accumulator Energy(J) Power(W) 000 1.60 45 0.4700 30 000000000000000000 0.000000000 0.000000000 001 1.56 45 0.4700 32 000000000000000000 0.000000000 0.000000000 Package[0] Cores Uncore Memory Platform Energy(J): 0.642406250 0.021968750 0.000000000 0.000000000 0.000000000 Power(W) : 0.642406250 0.021968750 0.000000000 0.000000000 0.000000000 ```

dmidecode -t 17

``` # dmidecode 3.4 Getting SMBIOS data from sysfs. SMBIOS 3.0.0 present. Handle 0x002A, DMI type 17, 40 bytes Memory Device Array Handle: 0x0028 Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 4 GB Form Factor: DIMM Set: None Locator: A1_DIMM0 Bank Locator: A1_BANK0 Type: DDR3 Type Detail: Synchronous Speed: 1600 MT/s Manufacturer: Samsung Serial Number: Asset Tag: 192274B6 Part Number: A1_AssetTagNum0 Rank: 1 Configured Memory Speed: 1066 MT/s Minimum Voltage: 1.35 V Maximum Voltage: 1.5 V Configured Voltage: 1.35 V Handle 0x002C, DMI type 17, 40 bytes Memory Device Array Handle: 0x0028 Error Information Handle: Not Provided Total Width: Unknown Data Width: 64 bits Size: No Module Installed Form Factor: DIMM Set: None Locator: A1_DIMM1 Bank Locator: A1_BANK1 Type: Unknown Type Detail: Synchronous ```

Only a single M471B5173QH0-YK0 RAM module is installed. BIOS also shows no timings information.

[cyring]

Is it possible you take screenshots of IMC Timings using Windows tools ? CPU-Z, OCCT, MemTweak,...

[cyring]

The memtest86 maintained version is pulling Timings from IMC registers.

The Airmont/Braswel decoder is not explicitly mentioned but I presume it works the same as in CoreFreq, using Silvermont/BayTrail IMC decoder: { 0xFFFF, 0x000A, "BayTrail IMC","", 0, poll_fsb_ct, poll_timings_ct, setup_nothing, poll_nothing}, // same as CedarTrail IMC

Function poll_timings_ct shows the same Registers addresses and bits used to decode the IMC:

• memtest86 static void poll_timings_ct(void)

• CoreFreq https://github.com/cyring/CoreFreq/blob/b7038862f0ca08e2a9a405173567a48b2ddea715/corefreqk.c#L5354

I'm wondering what Timings you will read from this memtest86 version ?

[antermin]

Tried CPU-Z on both PCs but it showed no IMC timings :

[cyring]

Tried CPU-Z on both PCs but it showed no IMC timings :

Unbelievable! CPU-Z is giving up.

Perhaps HWiNFO ?

[antermin]

This time it finally printed some information:

[cyring]

This time it finally printed some information:

So 11-11-11-28 are definitely confirmed as the configured IMC timing. I can't rely on the Silvermont decoder, although Airmont is a die shrink. New development is required. Unfortunately I have not found the Intel Registers datasheet volume 2 ref 332093. But HWINFO knows those Registers and maybe among its text output we may find the Memory MCH base address to decode from.

[antermin]

Are the following links of any help?

• Captured 2017-02, Document Number: 332093-002, N-series Intel® Pentium ® Processors and Intel ® Celeron ® Processors Datasheet – Volume 2 of 3, Dated February 2016
• Captured 2017-05, Document Number: 332093-001, N-series Intel® Pentium ® Processors and Intel ® Celeron ® Processors Datasheet – Volume 2 of 3, Dated April 2015

The above links are archives from Wayback Machine, but the one captured at a later date weirdly has an earlier date and different document number suffix. I am not sure about the differences in the actual content.

[cyring]

The above links are archives from Wayback Machine, but the one captured at a later date weirdly has an earlier date and different document number suffix. I am not sure about the differences in the actual content.

Well done. Thank you.

Can you pull, build and run the latest commits from the develop branch ?

The impacted timings (Z8000) are the followings:

tCL, tRCD, tRP, tRAS, tRRD, tRFC, tREFI
tRTPr, tWTPr, B2B, tCCD, tFAW, tCWL,
tsrRdTWr, tsrWrTRd,
tdrRdTRd, tdrRdTWr,
tdrWrTRd, tdrWrTWr,
CMD_Rate, tXS, tXP

Please provide the output of corefreq-cli -M

[antermin]

On N3050:

$ corefreq-cli -M
                              Airmont  [2280]                              
Controller #0                                               Single Channel 
 Bus Rate  5000 MT/s      Bus Speed 4999 MT/s          DDR3 Speed  800 MHz 

 Cha    CL  RCD   RP  RAS  RRD  RFC   WR RTPr WTPr  FAW  B2B  CWL CMD  REFI
  #0    11   11   11   14    5  384    0    7   24   24    0    8  2T     0
      ddWR drWR srWR ddRW drRW srRW ddRR drRR srRR ddWW drWW srWW CKE   ECC
  #0     0    7   19    0   10   10    0    7    0    0    6    0   0    0 

 DIMM Geometry for channel #0                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0     8    1     65536      1024           4096     A1_AssetTagNum0

[cyring]

tRAS: Row Activation Period. The minimal delay, in DRAM clocks, between ACT command and PRE command to same bank. At least equal to tRCD + tCWL + tCCD + tWR 0h -14 DRAM Clocks ...

According to specs, we just have to add 14

https://github.com/cyring/CoreFreq/blob/c8af79fee64acfbaffcfb67b6343f177a78ed573/corefreqd.c#L3268

    TIMING(mc, cha).tRAS = \
            RO(Proc)->Uncore.MC[mc].SLM.DTR1.Z8000.tRAS + 14;

[cyring]

I have fixed tWTPr where formula is now value + 15

B2B was changed into multiple tCCD conditions

tWWDR aka drWW deals with the reserved values 0 and 1

Both Airmont and Silvermont: DRMC register at offset 0xB is added to attempt decoding tCKE

You can now pull and try commit 0f70cde61624aa0c8f161eae564009747eb795a5

corefreq-cli -M output is welcomed.

[antermin]

$ corefreq-cli -M
                              Airmont  [2280]                              
Controller #0                                               Single Channel 
 Bus Rate  5000 MT/s      Bus Speed 4998 MT/s          DDR3 Speed  800 MHz 

 Cha    CL  RCD   RP  RAS  RRD  RFC   WR RTPr WTPr  FAW  B2B  CWL CMD  REFI
  #0    11   11   11   28    5  384    0    7   25   24    4    8  2T     0
      ddWR drWR srWR ddRW drRW srRW ddRR drRR srRR ddWW drWW srWW CKE   ECC
  #0     0    7   19    0   10   10    0    7    0    0    6    0   0    0 

 DIMM Geometry for channel #0                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0     8    1     65536      1024           4096     A1_AssetTagNum0

[cyring]

Hello,

Can you build and run this attached version which will print debug data in the kernel log.

When loading corefreqk.ko, log will contain many lines like below

(D-Unit)MCR:00[00000000]
(P-Unit)BIOS:00[00000000]

Remark: all values are hexadecimal

CoreFreq_develop.tar.gz

Edit: This dump has to be made on your system with two installed DIMMs. Please also provide the output of corefreq-cli -M

[antermin]

output.txt

[cyring]

I was expecting to find Timings of other B Registers. To my understanding, those of other DIMM or channel; but as shown below, the dump values are same as their default value in datasheet. It would mean B Registers are not updated since Processor reset and I can not make use of them.

(D-Unit)MCR:10[00000000]
(D-Unit)MCR:11[43402108]
(D-Unit)MCR:12[08c90320]
(D-Unit)MCR:13[00020508]
(D-Unit)MCR:14[06106108]
(D-Unit)MCR:15[8c063322]

For your information, currently, in dual channel mode, the Airmont decoder is just duplicating the first channel.

[cyring]

Using your two DIMMs setup, is it possible that you remove one DIMM and run the Registers dump again ?

I would like to find some meaningful changes among bits to declare when two modules are populated or not.

[antermin]

output-single-channel.txt

This time I only used one DIMM in that PC. If I put the module on channel B, it refuses to boot, so I put it on Channel A.

[cyring]

Here is the diff of single vs dual channels

(D-Unit)MCR:20[50030101]      | (D-Unit)MCR:20[50030001]
(D-Unit)MCR:21[0000003a]      | (D-Unit)MCR:21[000040a0]
(P-Unit)BIOS:06[418f0010]     | (P-Unit)BIOS:06[318f0010]

My understanding is that bit 30 of register BIOS CONFIG is specifying Dual Channel but also says implicitly two vs one DIMM

https://github.com/cyring/CoreFreq/blob/0f70cde61624aa0c8f161eae564009747eb795a5/intel_reg.h#L2860

• If DUAL_CH_DIS is set then platform is a Single channel with only one DIMM populated.
• If bit is clear then platform is Dual channels with a single DIMM per channel

In both cases your PC has only 2 DIMM slots. Is that true ?

[antermin]

Yeah, that PC has only 2 DIMM slots.

P.S. I also found that ECC (error correction code?) in the corefreq-cli -M output has changed when only 1 DIMM is populated.

[cyring]

Yeah, that PC has only 2 DIMM slots.

P.S. I also found that ECC (error correction code?) in the corefreq-cli -M output has changed when only 1 DIMM is populated.

In (P-Unit)BIOS:06[318f0010], bit 29 REG_EFF_ECC_EN of BIOS_CONFIG register is set when dual channels is enabled whereas in single mode, register value is 0x418f0010, and bit is clear.

ECC aggregation is happening in Daemon at these lines: https://github.com/cyring/CoreFreq/blob/0f70cde61624aa0c8f161eae564009747eb795a5/corefreqd.c#L3395

Aggregation was ok with Silvermont but apparently it is not OK with Airmont.

[cyring]

@antermin Hello,

You can now pull the new develop version 1.95.3 to check the IMC improvements in corefreq-cli -M

[cyring]

About the SMBIOS DIMM strings issue, can you show the output of XMRig ?

[cyring]

Does the latest code work with the IMC ? Should we close the issue ?

[antermin]

Sorry for the delay, here is the latest output:

                              Airmont  [2280]                              
Controller #0                                                Dual Channel  
 Bus Rate  3200 MT/s      Bus Speed 3199 MT/s          DDR3 Speed 1600 MHz 

 Cha    CL  RCD   RP  RAS  RRD  RFC   WR RTPr WTPr  FAW  B2B  CWL CMD  REFI
  #0    11   11   11   28    5  384    0    7   25   24    4    8  2T  3120
  #1    11   11   11   28    5  384    0    7   25   24    4    8  2T  3120
      ddWR drWR srWR ddRW drRW srRW ddRR drRR srRR ddWW drWW srWW CKE   ECC
  #0     0    6   19    0   10   10    0    7    0    0    6    0   0    0 
  #1     0    6   19    0   10   10    0    7    0    0    6    0   0    0 

 DIMM Geometry for channel #0                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0     8    2     65536      1024           8192     A1_AssetTagNum0
 DIMM Geometry for channel #1                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0     8    2     65536      1024           8192     A1_AssetTagNum0

And for xmrig:

$ ./xmrig --dry-run
[2023-02-14 21:01:34.601] hwloc auto configuration for algorithm "cn-heavy/0" failed.
 * ABOUT        XMRig/6.19.0 gcc/9.3.0
 * LIBS         libuv/1.44.2 OpenSSL/1.1.1s hwloc/2.9.0
 * HUGE PAGES   supported
 * 1GB PAGES    unavailable
 * CPU          Intel(R) Celeron(R) CPU N3150 @ 1.60GHz (1) 64-bit AES
                L2:2.0 MB L3:0.0 MB 4C/4T NUMA:1
 * MEMORY       0.6/15.3 GB (4%)
                A1_DIMM0: 8 GB DDR3 @ 1600 MHz A1_AssetTagNum0
                A1_DIMM1: 8 GB DDR3 @ 1600 MHz A1_AssetTagNum1
 * MOTHERBOARD  ASRock - N3150-NUC
 * DONATE       1%
 * ASSEMBLY     auto:intel
 * POOL #1      donate.v2.xmrig.com:3333 algo auto
 * COMMANDS     hashrate, pause, resume, results, connection
[2023-02-14 21:01:34.611]  config   OK

[cyring]

IMC now looks better. Only A1_AssetTagNum0 remains and xmrig shows to be also affected whereas dmidecode was not. In the future, other BIOS may reveal where the SMBIOS encoding issue is ? I guess we're OK with this release to close the original issue.

[cyring]

Controller #0                                                Dual Channel  
 Bus Rate  3200 MT/s      Bus Speed 3199 MT/s          DDR3 Speed 1600 MHz

Not sure from the above: are your DDR3 set at 800 or 1600 MHz ?

[antermin]

According to BIOS, both RAM modules are running at DDR3-1600.

(Based on Wikipedia's table, it probably means 800MHz and 1600 MT/s)

[cyring]

According to BIOS, both RAM modules are running at DDR3-1600.

(Based on Wikipedia's table, it probably means 800MHz and 1600 MT/s)

Can you please try the last fix and post the output of corefreq-cli -M ?

[antermin]

                              Airmont  [2280]                              
Controller #0                                                Dual Channel  
 Bus Rate  1600 MT/s      Bus Speed 1599 MT/s          DDR3 Speed  800 MHz 

 Cha    CL  RCD   RP  RAS  RRD  RFC   WR RTPr WTPr  FAW  B2B  CWL CMD  REFI
  #0    11   11   11   28    5  384    0    7   25   24    4    8  2T  1560
  #1    11   11   11   28    5  384    0    7   25   24    4    8  2T  1560
      ddWR drWR srWR ddRW drRW srRW ddRR drRR srRR ddWW drWW srWW CKE   ECC
  #0     0    6   19    0   10   10    0    7    0    0    6    0   0    0 
  #1     0    6   19    0   10   10    0    7    0    0    6    0   0    0 

 DIMM Geometry for channel #0                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0     8    2     65536      1024           8192     A1_AssetTagNum0
 DIMM Geometry for channel #1                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0     8    2     65536      1024           8192     A1_AssetTagNum0

[cyring]

@antermin Except the unsolved A1_AssetTagNum0 and missing timings in datasheet, the overall IMC decoder looks better.

[cyring]

Hello,

Celeron N3150 is now part of the CoreFreq Wiki

Let me know whenever you wish to refresh data.

Closing the issue.