Closed antermin closed 1 year ago
Most data appear accurate but I'm not sure about IMC timings.
Googleing HMA82GS6AFR8N-UH
I'm finding those factory values with a CL
of 17
But CoreFreq has decoded a CL
of 10
.
Can you please check and post the configured timings from BIOS or memtest86plus
?
BIOS reports CL 15 (15-15-15-35
).
Got it from "7th Generation Intel® Processor Families for U/Y Platforms and 8th Generation Intel® Processor Family for U Quad Core Datasheet, Volume 2 of 2" Order Number: 334662-005
tCL: Holds DDR timing parameter tCL. Read command to data delay in DCLK cycles. Supported range is 5-31.
Whenever I have clearly detected this architecture, I just have to add 5
to tCL
.
Thing I won't do with first Skylake.
I have checked and down to Skylake I'm supposed to also add 5
!
So I now have doubt about results from the past, plus I don't have access to such hardware to conduct non regression tests.
Let me know if you have various Skylake, Kabylake, Coffee Lake, type S, H, U ?
Skylake, Kabylake, Coffee Lake, type S, H, U
I have Coffee Lake-U (i3-8109U).
Other CPUs I have belong to other architectures such as i5-5200U and i5-7600.
Skylake, Kabylake, Coffee Lake, type S, H, U
I have Coffee Lake-U (i3-8109U).
Other CPUs I have belong to other architectures such as i5-5200U and i5-7600.
Yes please, could you post the output of corefreq-cli -s -n -B -n -k -n -M
based on latest develop
branch.
For my current Tiger Lake Mobile timings are the same with datasheet, Calculus issue seems limited to architectures from 6 to 8 generations.
Using latest commit, you can edit and change function SKL_IMC
as below and you should get the primary timings fixed.
https://github.com/cyring/CoreFreq/blob/0116ad71fb35dc5be1a2ff736137b1cd19fd995b/corefreqd.c#L4393
void SKL_IMC(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc))
{
TIMING(mc, cha).tCL = 5
+ RO(Proc)->Uncore.MC[mc].Channel[cha].SKL.ODT.tCL;
TIMING(mc, cha).tRCD = 5
+ RO(Proc)->Uncore.MC[mc].Channel[cha].SKL.Timing.tRP;
TIMING(mc, cha).tRP = 5
+ RO(Proc)->Uncore.MC[mc].Channel[cha].SKL.Timing.tRP;
TIMING(mc, cha).tRAS = 7
+ RO(Proc)->Uncore.MC[mc].Channel[cha].SKL.Timing.tRAS;
}
@svmlegacy Hello,
Based on latest develop
branch, could you post the output of your Celeron(R) CPU G3900
using corefreq-cli -k -n -B -n -M
Using latest commit, you can edit and change function
SKL_IMC
as below and you should get the primary timings fixed.
Thanks, now it shows:
Union Point [5904]
Controller #0 Dual Channel
Bus Rate 4000 MT/s Bus Speed 4004 MT/s DDR4 Speed 1333 MHz
Cha CL RCD RP RAS RRDs RRDl FAW WR RTPr WTPr CWL CKE CMD GEAR
#0 15 15 15 35 18 4 16 11 6 23 8 4 1T 0
#1 15 15 15 35 18 4 16 11 6 23 8 4 1T 0
sgRR dgRR drRR ddRR sgRW dgRW drRW ddRW sgWR dgWR drWR ddWR
#0 4 4 6 7 8 8 8 10 20 16 5 6
#1 4 4 7 7 8 8 8 10 19 16 5 6
sgWW dgWW drWW ddWW REFI RFC XS XP CPDED ECC
#0 4 4 7 7 5200 234 0 0 4 0
#1 4 4 7 7 5200 234 0 0 4 0
Thanks, now it shows:
Thank you.
I'm OK to change tCL
because datasheets specify that its first value within range is 5
But tRCD
(which is tRP
for SKL) and tRAS
are out of their range:
https://github.com/cyring/CoreFreq/blob/0116ad71fb35dc5be1a2ff736137b1cd19fd995b/intel_reg.h#L3688
To go further with source code:
I need screenshots of BIOS timings to validate values. What about the other timings ?
I will appreciate samples of SKL derivatives to be checked against BIOS.
@JohnAZoidberg Hello,
Based on latest develop branch, could you please post the output of your Core i5-8250U
using corefreq-cli -k -n -B -n -M
... and check if the DDR timings are the same with BIOS (preferably screenshots of it) ?
What about the other timings?
This is all my BIOS shows regarding memory timings:
What about the other timings?
This is all my BIOS shows regarding memory timings:
Thanks a lot. Can you post your Coffee Lake-U (i3-8109U) to check if the IMC timing values need exactly the same additions ?
Unsolved: regression risk on all Skylake decoders : Need large hardware scale testings : Postponed
On 1.93.1: