antermin
commented
1 year ago Why does it show Kaby Lake/UY? I think it should show Coffee Lake/U based on corefreqk.h?
Closed antermin closed 1 year ago
antermin
commented
1 year ago Why does it show Kaby Lake/UY? I think it should show Coffee Lake/U based on corefreqk.h?
antermin
commented
1 year ago Rebooted into BIOS and it shows: Memory Multiplier: 18 tCL: 17 tRCD: 17 tRASmin: 39 tCWL: 16 tCCDL: 6 tFAW: 26 tREFI: 9364 tRFC: 420 tRRD: 4 tRTP: 9 tWR: 18 Command Rate: 2n Round Trip Latency Optimization: Enabled
cyring
commented
1 year ago Why does it show
Kaby Lake/UY? I think it should showCoffee Lake/Ubased oncorefreqk.h?
Yes it should have been detected as "Coffee Lake/U"
https://github.com/cyring/CoreFreq/blob/0116ad71fb35dc5be1a2ff736137b1cd19fd995b/corefreqk.h#L4079
Need to debug.
cyring
commented
1 year ago Rebooted into BIOS and it shows: Memory Multiplier: 18 tCL: 17 tRCD: 17 tRASmin: 39 tCWL: 16 tCCDL: 6 tFAW: 26 tREFI: 9364 tRFC: 420 tRRD: 4 tRTP: 9 tWR: 18 Command Rate: 2n Round Trip Latency Optimization: Enabled
Indeed with i3-8109U, CoreFreq decoder barely results with the same IMC timings as i7-7567U
Without patch they both result as 10-10-10-30. Need to debug.
cyring
commented
1 year ago Why does it show
Kaby Lake/UY? I think it should showCoffee Lake/Ubased oncorefreqk.h?Yes it should have been detected as
"Coffee Lake/U"https://github.com/cyring/CoreFreq/blob/0116ad71fb35dc5be1a2ff736137b1cd19fd995b/corefreqk.h#L4079
Need to debug.
I found the issue: processor string has to be part of this list.
https://github.com/cyring/CoreFreq/blob/0116ad71fb35dc5be1a2ff736137b1cd19fd995b/corefreqk.h#L4127
cyring
commented
1 year ago Why does it show
Kaby Lake/UY? I think it should showCoffee Lake/Ubased oncorefreqk.h?
Please pull the latest commit of develop branch and try the codename fix.
cyring
commented
1 year ago Codename fixed.
antermin
commented
1 year ago Sorry for the long delay.
I have switched to 2x HMA82GS6AFR8N-UH modules.
BIOS shows: Memory Multiplier: 18 tCL: 17 tRCD: 17 tRASmin: 39 tCWL: 16 tCCDL: 6 tFAW: 26 tREFI: 9364 tRFC: 420 tRRD: 4 tRTP: 9 tWR: 18 Command Rate: 2n Round Trip Latency Optimization: Enabled
$ corefreq-cli -s -n -m -n -B -n -M -n -C 1
Processor [Intel(R) Core(TM) i3-8109U CPU @ 3.00GHz]
|- Architecture [Coffee Lake/U]
|- Vendor ID [GenuineIntel]
|- Microcode [0x000000f0]
|- Signature [ 06_8E]
|- Stepping [ 10]
|- Online CPU [ 4/ 4]
|- Base Clock [100.007]
|- Frequency (MHz) Ratio
Min 400.03 < 4 >
Max 3000.21 < 30 >
|- Factory [100.000]
3000 [ 30 ]
|- Performance
|- P-State
TGT 400.03 < 4 >
|- HWP
Min 400.03 < 4 >
Max 3600.26 < 36 >
TGT AUTO < 0 >
|- Turbo Boost [ UNLOCK]
1C 3600.26 < 36 >
2C 3600.26 < 36 >
3C 3600.26 < 36 >
4C 3600.26 < 36 >
|- Uncore [ UNLOCK]
Min 400.03 < 4 >
Max 3300.23 < 33 >
|- TDP Level < 0:3 >
|- Programmable [ UNLOCK]
|- Configuration [ UNLOCK]
|- Turbo Activation [ UNLOCK]
Nominal 3000.21 [ 30 ]
Level1 1900.13 [ 19 ]
Turbo 2900.21 < 29 >
Instruction Set Extensions
|- 3DNow!/Ext [N/N] ADX [Y] AES [Y] AVX/AVX2 [Y/Y]
|- AVX512-F [N] AVX512-DQ [N] AVX512-IFMA [N] AVX512-PF [N]
|- AVX512-ER [N] AVX512-CD [N] AVX512-BW [N] AVX512-VL [N]
|- AVX512-VBMI [N] AVX512-VBMI2 [N] AVX512-VNNI [N] AVX512-ALG [N]
|- AVX512-VPOP [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N]
|- AVX512-BF16 [N] AVX-VNNI-VEX [N] MOVDIRI [N] MOVDIR64B [N]
|- BMI1/BMI2 [Y/Y] CLWB [N] CLFLUSH [Y] CLFLUSH-OPT [Y]
|- CLAC-STAC [Y] CMOV [Y] CMPXCHG8B [Y] CMPXCHG16B [Y]
|- F16C [Y] FPU [Y] FXSR [Y] LAHF-SAHF [Y]
|- ENQCMD [N] GFNI [N] OSPKE [N] WAITPKG [N]
|- MMX/Ext [Y/N] MON/MWAITX [Y/N] MOVBE [Y] PCLMULQDQ [Y]
|- POPCNT [Y] RDRAND [Y] RDSEED [Y] RDTSCP [Y]
|- SEP [Y] SHA [N] SSE [Y] SSE2 [Y]
|- SSE3 [Y] SSSE3 [Y] SSE4.1/4A [Y/N] SSE4.2 [Y]
|- SERIALIZE [N] SYSCALL [Y] RDPID [N] SGX [Y]
|- VAES [N] VPCLMULQDQ [N] PREFETCH/W [Y] LZCNT [Y]
Features
|- 1 GB Pages Support 1GB-PAGES [Capable]
|- Advanced Configuration & Power Interface ACPI [Capable]
|- Advanced Programmable Interrupt Controller APIC [Capable]
|- APIC Timer Invariance ARAT [Capable]
|- Core Multi-Processing CMP Legacy [Missing]
|- L1 Data Cache Context ID CNXT-ID [Missing]
|- Direct Cache Access DCA [Missing]
|- Debugging Extension DE [Capable]
|- Debug Store & Precise Event Based Sampling DS, PEBS [Capable]
|- CPL Qualified Debug Store DS-CPL [Capable]
|- 64-Bit Debug Store DTES64 [Capable]
|- Fast Short REP CMPSB FSRC [Missing]
|- Fast Short REP MOVSB FSRM [Missing]
|- Fast Short REP STOSB FSRS [Missing]
|- Fast Zero-length REP MOVSB FZRM [Missing]
|- Fast-String Operation ERMS [Capable]
|- Fused Multiply Add FMA | FMA4 [Capable]
|- Hardware Feedback Interface HFI [Missing]
|- Hardware Lock Elision HLE [Missing]
|- History Reset HRESET [Missing]
|- Hybrid part processor HYBRID [Missing]
|- Instruction Based Sampling IBS [Missing]
|- Instruction INVPCID INVPCID [Capable]
|- Long Mode 64 bits IA64 | LM [Capable]
|- Linear Address Masking LAM [Missing]
|- LightWeight Profiling LWP [Missing]
|- Machine-Check Architecture MCA [Capable]
|- Memory Protection Extensions MPX [Capable]
|- Model Specific Registers MSR [Capable]
|- Memory Type Range Registers MTRR [Capable]
|- OS-Enabled Ext. State Management OSXSAVE [Capable]
|- Physical Address Extension PAE [Capable]
|- Page Attribute Table PAT [Capable]
|- Pending Break Enable PBE [Capable]
|- Platform Configuration PCONFIG [Missing]
|- Process Context Identifiers PCID [Capable]
|- Perfmon and Debug Capability PDCM [Capable]
|- Page Global Enable PGE [Capable]
|- Page Size Extension PSE [Capable]
|- 36-bit Page Size Extension PSE36 [Capable]
|- Processor Serial Number PSN [Missing]
|- Write Data to a Processor Trace Packet PTWRITE [Missing]
|- Resource Director Technology/PQE RDT-A [Missing]
|- Resource Director Technology/PQM RDT-M [Missing]
|- Restricted Transactional Memory RTM [Missing]
|- Safer Mode Extensions SMX [Missing]
|- Self-Snoop SS [Capable]
|- Supervisor-Mode Access Prevention SMAP [Capable]
|- Supervisor-Mode Execution Prevention SMEP [Capable]
|- Thread Director TD [Missing]
|- Time Stamp Counter TSC [Invariant]
|- Time Stamp Counter Deadline TSC-DEADLINE [Capable]
|- TSX Force Abort MSR Register TSX-ABORT [Capable]
|- TSX Suspend Load Address Tracking TSX-LDTRK [Missing]
|- User-Mode Instruction Prevention UMIP [Missing]
|- Virtual Mode Extension VME [Capable]
|- Virtual Machine Extensions VMX [Capable]
|- Write Back & Do Not Invalidate Cache WBNOINVD [Missing]
|- Extended xAPIC Support x2APIC [ x2APIC]
|- Execution Disable Bit Support XD-Bit [Capable]
|- XSAVE/XSTOR States XSAVE [Capable]
|- xTPR Update Control xTPR [Capable]
Mitigation mechanisms
|- Indirect Branch Restricted Speculation IBRS [ Enable]
|- Indirect Branch Prediction Barrier IBPB [Capable]
|- Single Thread Indirect Branch Predictor STIBP [Capable]
|- Speculative Store Bypass Disable SSBD [Capable]
|- Writeback & invalidate the L1 data cache L1D-FLUSH [Capable]
|- Hypervisor - No flush L1D on VM entry L1DFL_VMENTRY_NO [Capable]
|- Arch - Buffer Overwriting MD-CLEAR [Capable]
|- Arch - No Rogue Data Cache Load RDCL_NO [Capable]
|- Arch - Enhanced IBRS IBRS_ALL [Capable]
|- Arch - Return Stack Buffer Alternate RSBA [ Enable]
|- Arch - No Speculative Store Bypass SSB_NO [Capable]
|- Arch - No Microarchitectural Data Sampling MDS_NO [Capable]
|- Arch - No TSX Asynchronous Abort TAA_NO [Capable]
|- Arch - No Page Size Change MCE PSCHANGE_MC_NO [Capable]
|- Arch - STLB QoS STLB [ Unable]
|- Arch - Functional Safety Island FuSa [ Unable]
|- Arch - RSM in CPL0 only RSM [ Unable]
|- Arch - Split Locked Access Exception SPLA [ Unable]
|- Arch - Snoop Filter QoS Mask SNOOP_FILTER [ Unable]
|- Arch - No Fast Predictive Store Forwarding PSFD [ Unable]
|- Arch - Data Operand Independent Timing Mode DOITM [ Unable]
|- Arch - Not affected by SBDR or SSDP SBDR_SSDP_NO [Capable]
|- Arch - No Fill Buffer Stale Data Propagator FBSDP_NO [Capable]
|- Arch - No Primary Stale Data Propagator PSDP_NO [Capable]
|- Arch - Overwrite Fill Buffer values FB_CLEAR [Capable]
|- Arch - Special Register Buffer Data Sampling SRBDS [Capable]
|- RDRAND and RDSEED mitigation RNGDS [Capable]
|- Restricted Transactional Memory RTM [Capable]
|- Verify Segment for Writing instruction VERW [Capable]
|- Arch - Restricted RSB Alternate RRSBA [Capable]
|- Arch - No Branch Target Injection BHI_NO [Capable]
|- Arch - Legacy xAPIC Disable XAPIC_DIS [ Unable]
|- Arch - No Post-Barrier Return Stack Buffer PBRSB_NO [Capable]
|- Arch - IPRED disabled for CPL3 IPRED_DIS_U [ Unable]
|- Arch - IPRED disabled for CPL0/1/2 IPRED_DIS_S [ Unable]
|- Arch - RRSBA disabled for CPL3 RRSBA_DIS_U [ Unable]
|- Arch - RRSBA disabled for CPL0/1/2 RRSBA_DIS_S [ Unable]
|- Arch - BHI disabled for CPL0/1/2 BHI_DIS_S [ Unable]
|- No MXCSR Configuration Dependent Timing MCDT_NO [ Unable]
Security Features
|- CPUID Key Locker KL [Missing]
|- AES Key Locker instructions AESKLE [Missing]
|- AES Wide Key Locker instructions WIDE_KL [Missing]
|- Software Guard SGX1 Extensions SGX1 [Missing]
|- Software Guard SGX2 Extensions SGX2 [Missing]
Technologies
|- Data Cache Unit
|- L1 Prefetcher L1 HW < ON>
|- L1 IP Prefetcher L1 HW IP < ON>
|- L2 Prefetcher L2 HW < ON>
|- L2 Line Prefetcher L2 HW CL < ON>
|- System Management Mode SMM-Dual [ ON]
|- Hyper-Threading HTT [ ON]
|- SpeedStep EIST < ON>
|- Dynamic Acceleration IDA [ ON]
|- Turbo Boost TURBO < ON>
|- Energy Efficiency Optimization EEO < ON>
|- Race To Halt Optimization R2H < ON>
|- Watchdog Timer TCO <OFF>
|- Virtualization VMX [ ON]
|- I/O MMU VT-d [ ON]
|- Version [ 1.0]
|- Hypervisor [OFF]
|- Vendor ID [ N/A]
Performance Monitoring
|- Version PM [ 4]
|- Counters: General Fixed
| { 4, 0, 0 } x 48 bits 3 x 48 bits
|- Enhanced Halt State C1E <OFF>
|- C1 Auto Demotion C1A < ON>
|- C3 Auto Demotion C3A <OFF>
|- C1 UnDemotion C1U < ON>
|- C3 UnDemotion C3U < ON>
|- C6 Core Demotion CC6 <OFF>
|- C6 Module Demotion MC6 <OFF>
|- Legacy Frequency ID control FID [OFF]
|- Legacy Voltage ID control VID [OFF]
|- P-State Hardware Coordination Feedback MPERF/APERF [ ON]
|- Hardware Duty Cycling HDC <OFF>
|- Package C-States
|- Configuration Control CONFIG [ LOCK]
|- Lowest C-State LIMIT < C0>
|- I/O MWAIT Redirection IOMWAIT <Disable>
|- Max C-State Inclusion RANGE < C8>
|- Core C-States
|- C-States Base Address BAR [ 0x1814]
|- ACPI Processor C-States _CST [ 3]
|- MONITOR/MWAIT
|- State index: #0 #1 #2 #3 #4 #5 #6 #7
|- Sub C-State: 0 2 1 2 4 1 1 1
|- Core Cycles [Capable]
|- Instructions Retired [Capable]
|- Reference Cycles [Capable]
|- Last Level Cache References [Capable]
|- Last Level Cache Misses [Capable]
|- Branch Instructions Retired [Capable]
|- Branch Mispredicts Retired [Capable]
|- Top-down slots Counter [Capable]
|- Processor Performance Control _PCT [ Enable]
|- Performance Supported States _PSS [ 0]
|- Performance Present Capabilities _PPC [ 0]
Power, Current & Thermal
|- Temperature Offset:Junction TjMax < 0:100 C>
|- Clock Modulation ODCM <Disable>
|- DutyCycle [ 0.00%]
|- Power Management PWR MGMT [ LOCK]
|- Energy Policy Bias Hint < 6>
|- Energy Policy HWP EPP < 128>
|- Digital Thermal Sensor DTS [Capable]
|- Power Limit Notification PLN [Capable]
|- Package Thermal Management PTM [Capable]
|- Thermal Monitor 1 TM1 [ Enable]
|- Thermal Monitor 2 TM2 [Capable]
|- Thermal Design Power TDP [ 28 W]
|- Minimum Power Min [Missing]
|- Maximum Power Max [Missing]
|- Thermal Design Power Package < Enable>
|- Power Limit PL1 < 28 W>
|- Time Window TW1 < 1m04s>
|- Power Limit PL2 < 50 W>
|- Time Window TW2 < 2 ms>
|- Thermal Design Power Core <Disable>
|- Power Limit PL1 < 0 W>
|- Time Window TW1 < 976 us>
|- Thermal Design Power Uncore <Disable>
|- Power Limit PL1 < 0 W>
|- Time Window TW1 < 976 us>
|- Thermal Design Power DRAM [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 976 us]
|- Thermal Design Power Platform < Enable>
|- Power Limit PL1 < 92 W>
|- Time Window TW1 < 28 s>
|- Power Limit PL2 < 83 W>
|- Time Window TW2 < 976 us>
|- Electrical Design Current EDC [Missing]
|- Thermal Design Current TDC [Missing]
|- Core Thermal Point
|- DTS Threshold #1 Threshold [Missing]
|- DTS Threshold #2 Threshold [Missing]
|- Package Thermal Point
|- DTS Threshold #1 Threshold [Missing]
|- DTS Threshold #2 Threshold [Missing]
|- Units
|- Power watt [ 0.125000000]
|- Energy joule [ 0.000061035]
|- Window second [ 0.000976562]
CPU Pkg Apic Core/Thread Caches (w)rite-Back (i)nclusive
# ID ID ID ID L1-Inst Way L1-Data Way L2 Way L3 Way
000:BSP 0 0 0 32768 8 32768 8 262144 4 4194304 16 i
001: 0 2 1 0 32768 8 32768 8 262144 4 4194304 16 i
002: 0 1 0 1 32768 8 32768 8 262144 4 4194304 16 i
003: 0 3 1 1 32768 8 32768 8 262144 4 4194304 16 i
[ 0] Intel Corp.
[ 1] BECFL357.86A.0090.2022.0916.1942
[ 2] 09/16/2022
[ 3] Intel(R) Client Systems
[ 4] NUC8i3BEH
[ 5] J72753-308
[ 6] G---9---0---
[ 7] BOXNUC8i3BEH
[ 8] BE
[ 9] Intel Corporation
[10] NUC8BEB
[11] J72693-309
[12] G---9---0---
[13] Number Of Devices:2\Maximum Capacity:33554432 kilobytes
[14] SODIMM1\Memory Channel A
[15] SODIMM2\Memory Channel B
[16]
[17]
[18] SK Hynix
[19] SK Hynix
[20]
[21]
[22] HMA82GS6AFR8N-UH
[23] HMA82GS6AFR8N-UH
[24]
[25]
Cannon Point [3ECC]
Controller #0 Dual Channel
Bus Rate 4000 MT/s Bus Speed 3999 MT/s DDR4 Speed 1333 MHz
Cha CL RCDr RCDw RP RAS RRDs RRDl FAW WR RTPr WTPr CWL CKE CMD
#0 10 10 10 10 28 18 4 16 11 6 23 8 4 1T
#1 10 10 10 10 28 18 4 16 11 6 23 8 4 1T
sgRR dgRR drRR ddRR sgRW dgRW drRW ddRW sgWR dgWR drWR ddWR
#0 4 4 6 7 8 8 8 10 19 16 5 6
#1 4 4 7 7 8 8 10 10 19 16 5 6
sgWW dgWW drWW ddWW REFI RFC XS XP CPDED GEAR ECC
#0 4 4 7 7 5054 234 0 0 4 0 0
#1 4 4 7 7 5054 234 0 0 4 0 0
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0 16 2 65536 1024 16384 HMA82GS6AFR8N-UH
#1
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0 16 2 65536 1024 16384 HMA82GS6AFR8N-UH
#1
CPU Freq(MHz) VID Vcore TMP(C) Accumulator Energy(J) Power(W)
000 258.02 0 0.0000 44 000000000000000000 0.000000000 0.000000000
001 196.74 5811 0.7094 44 000000000000000000 0.000000000 0.000000000
002 227.13 0 0.0000 44 000000000000000000 0.000000000 0.000000000
003 200.24 0 0.0000 44 000000000000000000 0.000000000 0.000000000
Package[0] Cores Uncore Memory Platform
Energy(J): 2.596435547 0.254394531 0.000000000 0.683837891 0.000000000
Power(W) : 2.596435547 0.254394531 0.000000000 0.683837891 0.000000000(Edit: The above is output of 1.95.5, without the SKL_IMC patch)
antermin
commented
1 year ago Another question: why are the entries for Power(W) same as Energy(J)?
Package[0] Cores Uncore Memory Platform
Energy(J): 2.596435547 0.254394531 0.000000000 0.683837891 0.000000000
Power(W) : 2.596435547 0.254394531 0.000000000 0.683837891 0.000000000Another question: why are the entries for Power(W) same as Energy(J)?
Because the default period is one second
Go to Settings > Interval and change it to another period and the "Power, Joule" math formula will self-adapt
cyring
commented
1 year ago Going through the online datasheets from 6 to 8/9 generation, I don't find a difference in bits layout and definition of, for example, the CAS Latency tCL
Skylake decoder has been implemented a while a go and the decoded timings by CoreFreq were matching BIOS.
For some reasons Coffee Lake don't match anymore! Firmware update ?
antermin
commented
1 year ago Using HWiNFO64 v7.42, it seems that the behavior is the same as this, i.e. Memory Controller is observed to change memory frequencies and timings on the fly.
Most of the time it stays in 10-10-10-28, but sometimes it will switch to 17-17-17-39.
cyring
commented
1 year ago Most of the time it stays in 10-10-10-28, but sometimes it will switch to 17-17-17-39.
Awesome observation. I think we need the help of Intel to understand what's going on; if some additionnal bits have to be taken into consideration ?
cyring
commented
1 year ago I had encountered issues where Resumed from suspend in S3 was not restoring some settings as expected. Don't you ?
antermin
commented
1 year ago May I know what do you mean by "some settings"? Settings in CoreFreq or in other places?
When the NUC is resumed from suspend in S3, I can log in and resume the desktop session without any issue.
cyring
commented
1 year ago May I know what do you mean by "some settings"? Settings in CoreFreq or in other places?
When the NUC is resumed from suspend in S3, I can log in and resume the desktop session without any issue.
By settings I meant registers: I had the Turbo frequencies MSR not restored as I wrote them previously. Other cases, I found P-States not restored. But I've not faced such DRAM timings issue.
antermin
commented
1 year ago Can you please tell me how to check whether Turbo frequencies MSR and P-States are correctly restored, so that I can check whether I have the same issues?
cyring
commented
1 year ago 
6C up to 1C ratios and the TGT P-State26) + one bin = 27
systemctl suspend
antermin
commented
1 year ago I followed this and have verified that CoreFreq is used as the Clock Source, CPU Freq and CPU Idle drive.
However, for the first step I can only adjust TGT from 29 to 31. When I try to adjust 1C, 2C, 3C, 4C to 37, selecting a higher bin has no effect, and it stays at 36.
cyring
commented
1 year ago ## kernel prequisities
cat /proc/cmdline
msr.allow_writes=on
## read the turbo register
rdmsr -ax 0x1ad
24242424
## add one bin to each ratio
wrmsr -a 0x1ad 0x25252525
## check the written value
rdmsr -ax 0x1ad Weird - I have already allowed writing MSR:
rw initrd=\intel-ucode.img initrd=\initramfs-linux.img iomem=relaxed intel_iommu=on i915.enable_guc=0 msr.allow_writes=on
But it always shows the following, the turbo registers are not changed after I attempted to add one bin to each ratio:
24242424
24242424
24242424
24242424the turbo registers are not changed after I attempted to add one bin to each ratio:
Because that MSR is locked. Despite CPUID says the contrary ; reflected as Unlock in Processor window. I had met that case with other Mobile processors.
cyring
commented
1 year ago There's nothing more I'm finding about the fluctuating IMC data. Perhaps one-day if I can put my hands on such hardware, I may show up with enhancements... Thank you for your contributions.
cyring
commented
1 year ago Here's one answer provided by our friend ChatGPT
... modern memory controllers are designed to be dynamic and adaptive, and they can adjust memory frequencies and timings on the fly based on the system's workload and power consumption.
For example, if the system is running memory-intensive applications such as video editing or gaming, the memory controller may increase the frequency and tighten the timings to provide better performance. On the other hand, if the system is running less demanding applications, the memory controller may decrease the frequency and loosen the timings to save power and reduce heat.
This dynamic adjustment is typically handled by the memory controller firmware and is transparent to the operating system and applications...
Edit: and the closest definition I'm finding is bit QCLK_GV_DIS (Dynamic Memory Frequency Change Disable) but it is specified since 10th generation in Capabilities C (CAPID0_C_0_0_0_PCI) — Offset ECh
https://github.com/cyring/CoreFreq/blob/8eae64ec2566d07679155f3213a822bc04ab954f/intel_reg.h#L4773
On
0116ad7+SKL_IMCpatch: