Closed justanerd closed 1 year ago
Nice. This is the first received report about Raptor Lake
.
Globally CoreFreq support appears good. Especially the Hybrid topology.
To complete with the IMC Memory Controller, I will need you post the output of lspci -nn
to match the PCH device ID
I'm also observing a Target Ratio of 70
which means I will increase the MAX_FREQ_HZ
above 7 GHz
in Makefile
Vcore is supplied for PCore but not computed yet with the Ecore yet, although we see a VID
value.
This can be improved and I will be back with more testings to calibrate the Ecore voltage formula.
lspci -nn
00:00.0 Host bridge [0600]: Intel Corporation Device [8086:a700] (rev 01)
00:01.0 PCI bridge [0604]: Intel Corporation Device [8086:a70d] (rev 01)
00:01.1 PCI bridge [0604]: Intel Corporation Device [8086:a72d] (rev 01)
00:02.0 VGA compatible controller [0300]: Intel Corporation Raptor Lake-S GT1 [UHD Graphics 770] [8086:a780] (rev 04)
00:06.0 PCI bridge [0604]: Intel Corporation Device [8086:a74d] (rev 01)
00:14.0 USB controller [0c03]: Intel Corporation Alder Lake-S PCH USB 3.2 Gen 2x2 XHCI Controller [8086:7ae0] (rev 11)
00:14.2 RAM memory [0500]: Intel Corporation Alder Lake-S PCH Shared SRAM [8086:7aa7] (rev 11)
00:15.0 Serial bus controller [0c80]: Intel Corporation Alder Lake-S PCH Serial IO I2C Controller #0 [8086:7acc] (rev 11)
00:15.1 Serial bus controller [0c80]: Intel Corporation Alder Lake-S PCH Serial IO I2C Controller #1 [8086:7acd] (rev 11)
00:15.2 Serial bus controller [0c80]: Intel Corporation Alder Lake-S PCH Serial IO I2C Controller #2 [8086:7ace] (rev 11)
00:15.3 Serial bus controller [0c80]: Intel Corporation Alder Lake-S PCH Serial IO I2C Controller #3 [8086:7acf] (rev 11)
00:16.0 Communication controller [0780]: Intel Corporation Alder Lake-S PCH HECI Controller #1 [8086:7ae8] (rev 11)
00:17.0 SATA controller [0106]: Intel Corporation Alder Lake-S PCH SATA Controller [AHCI Mode] [8086:7ae2] (rev 11)
00:19.0 Serial bus controller [0c80]: Intel Corporation Alder Lake-S PCH Serial IO I2C Controller #4 [8086:7afc] (rev 11)
00:19.1 Serial bus controller [0c80]: Intel Corporation Alder Lake-S PCH Serial IO I2C Controller #5 [8086:7afd] (rev 11)
00:1a.0 PCI bridge [0604]: Intel Corporation Device [8086:7ac8] (rev 11)
00:1b.0 PCI bridge [0604]: Intel Corporation Device [8086:7ac0] (rev 11)
00:1b.4 PCI bridge [0604]: Intel Corporation Device [8086:7ac4] (rev 11)
00:1c.0 PCI bridge [0604]: Intel Corporation Alder Lake-S PCH PCI Express Root Port #1 [8086:7ab8] (rev 11)
00:1c.2 PCI bridge [0604]: Intel Corporation Device [8086:7aba] (rev 11)
00:1c.3 PCI bridge [0604]: Intel Corporation Device [8086:7abb] (rev 11)
00:1d.0 PCI bridge [0604]: Intel Corporation Alder Lake-S PCH PCI Express Root Port #9 [8086:7ab0] (rev 11)
00:1d.4 PCI bridge [0604]: Intel Corporation Alder Lake-S PCH PCI Express Root Port #13 [8086:7ab4] (rev 11)
00:1f.0 ISA bridge [0601]: Intel Corporation Z690 Chipset LPC/eSPI Controller [8086:7a84] (rev 11)
00:1f.3 Audio device [0403]: Intel Corporation Alder Lake-S HD Audio Controller [8086:7ad0] (rev 11)
00:1f.4 SMBus [0c05]: Intel Corporation Alder Lake-S PCH SMBus Controller [8086:7aa3] (rev 11)
00:1f.5 Serial bus controller [0c80]: Intel Corporation Alder Lake-S PCH SPI Controller [8086:7aa4] (rev 11)
01:00.0 VGA compatible controller [0300]: NVIDIA Corporation AD102 [GeForce RTX 4090] [10de:2684] (rev a1)
01:00.1 Audio device [0403]: NVIDIA Corporation AD102 High Definition Audio Controller [10de:22ba] (rev a1)
02:00.0 Non-Volatile memory controller [0108]: Phison Electronics Corporation E12 NVMe Controller [1987:5012] (rev 01)
03:00.0 Non-Volatile memory controller [0108]: Samsung Electronics Co Ltd NVMe SSD Controller SM981/PM981/PM983 [144d:a808]
04:00.0 Non-Volatile memory controller [0108]: Samsung Electronics Co Ltd NVMe SSD Controller SM981/PM981/PM983 [144d:a808]
06:00.0 Non-Volatile memory controller [0108]: Samsung Electronics Co Ltd NVMe SSD Controller SM981/PM981/PM983 [144d:a808]
07:00.0 Ethernet controller [0200]: Aquantia Corp. Device [1d6a:14c0] (rev 03)
08:00.0 Ethernet controller [0200]: Intel Corporation Ethernet Controller I225-V [8086:15f3] (rev 03)
09:00.0 Network controller [0280]: Intel Corporation Wi-Fi 6 AX210/AX211/AX411 160MHz [8086:2725] (rev 1a)
0a:00.0 PCI bridge [0604]: Intel Corporation Thunderbolt 4 Bridge [Maple Ridge 4C 2020] [8086:1136] (rev 02)
0b:00.0 PCI bridge [0604]: Intel Corporation Thunderbolt 4 Bridge [Maple Ridge 4C 2020] [8086:1136] (rev 02)
0b:01.0 PCI bridge [0604]: Intel Corporation Thunderbolt 4 Bridge [Maple Ridge 4C 2020] [8086:1136] (rev 02)
0b:02.0 PCI bridge [0604]: Intel Corporation Thunderbolt 4 Bridge [Maple Ridge 4C 2020] [8086:1136] (rev 02)
0b:03.0 PCI bridge [0604]: Intel Corporation Thunderbolt 4 Bridge [Maple Ridge 4C 2020] [8086:1136] (rev 02)
0c:00.0 USB controller [0c03]: Intel Corporation Thunderbolt 4 NHI [Maple Ridge 4C 2020] [8086:1137]
0e:00.0 USB controller [0c03]: Intel Corporation Thunderbolt 4 USB Controller [Maple Ridge 4C 2020] [8086:1138]
10:00.0 Non-Volatile memory controller [0108]: Samsung Electronics Co Ltd NVMe SSD Controller SM981/PM981/PM983 [144d:a808]
You can now try to decode the IMC from the latest develop
commit.
Warmly suggest you to save your files before shooting the driver.
If it running OK, please refresh your previous output, above, especially corefreq-cli -M
Thank you
Looks good:
Intel 700 Series [A700]
Controller #0 Dual Channel
Bus Rate 4500 MHz Bus Speed 4492 MHz DDR5 Speed 3494 MHz
Cha CL RCD RP RAS RRDs RRDl FAW WR RTPr WTPr CWL CKE CMD GEAR
#0 32 40 40 28 6 8 16 10 10 40 26 4 1T 2
#1 32 40 40 28 6 8 16 10 10 40 26 4 1T 2
sgRR dgRR drRR ddRR sgRW dgRW drRW ddRW sgWR dgWR drWR ddWR
#0 14 8 16 18 18 18 22 24 76 46 10 10
#1 14 8 16 18 18 18 22 24 76 46 10 10
sgWW dgWW drWW ddWW REFI RFC XS XP CPDED ECC
#0 36 8 14 14 66666 400 1023 4 18 0
#1 36 8 14 14 66666 400 1023 4 18 0
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 8 1 131072 1024 8192 F5-7800J3646H16G
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 8 1 131072 1024 8192 F5-7800J3646H16G
Controller #1 Dual Channel
Bus Rate 4500 MHz Bus Speed 4492 MHz DDR5 Speed 3494 MHz
Cha CL RCD RP RAS RRDs RRDl FAW WR RTPr WTPr CWL CKE CMD GEAR
#0 32 40 40 28 6 8 16 10 10 40 26 4 1T 2
#1 32 40 40 28 6 8 16 10 10 40 26 4 1T 2
sgRR dgRR drRR ddRR sgRW dgRW drRW ddRW sgWR dgWR drWR ddWR
#0 14 8 16 18 18 18 22 24 76 46 10 10
#1 14 8 16 18 18 18 22 24 76 46 10 10
sgWW dgWW drWW ddWW REFI RFC XS XP CPDED ECC
#0 36 8 14 14 66666 400 1023 4 18 0
#1 36 8 14 14 66666 400 1023 4 18 0
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 8 1 131072 1024 8192 F5-7800J3646H16G
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 8 1 131072 1024 8192 F5-7800J3646H16G
Do you have 4 sticks of 8GB DIMM ?
No, 2 16 GB Sticks.
On Fri, Jan 20, 2023 at 2:42 PM CyrIng @.***> wrote:
Do you have 4 sticks of 8GB DIMM ?
— Reply to this email directly, view it on GitHub https://github.com/cyring/CoreFreq/issues/404#issuecomment-1398415221, or unsubscribe https://github.com/notifications/unsubscribe-auth/AAF7RJLB7KVLMYJTXL2CF63WTKI47ANCNFSM6AAAAAAUAD455U . You are receiving this because you authored the thread.Message ID: @.***>
Thing I did not notice with Alder Lake i9-12900K but later with AMD Zen3+ is the DDR5 in quad channels.
Here 13900K has 2 x DDR5 DIMMs in quad channels mode (thing you may read in other Windows tools) but contrary to AMD, Intel seems to split each DIMM in 2 registers sets, same settings but half size. One for each 32 bits mode. This could be the trick they used to keep the registers specs the same as previous arch: Alder Lake.
So facing DDR5, CoreFreq algorithm will have to sacrifice one every two controllers; let's say the odd identifiers and alter Geometry to reflect the true size. Bank
is the good candidate.
Hello,
Can you give a quick test to this version and post the Memory Controller output ?
In case you have an Alder Lake, the same test will help for non regression.
Thank you
Meanwhile I have completed the support list of Chipsets: can you pull the develop
branch and refresh your output, especially IMC.
Thank you
Processor [13th Gen Intel(R) Core(TM) i9-13900K]
|- Architecture [Raptor Lake]
|- Vendor ID [GenuineIntel]
|- Microcode [0x0000010f]
|- Signature [ 06_B7]
|- Stepping [ 1]
|- Online CPU [ 32/ 32]
|- Base Clock [ 99.836]
|- Frequency (MHz) Ratio
Min 798.70 < 8 >
Max 2995.11 < 30 >
|- Factory [100.000]
3000 [ 30 ]
|- Performance
|- P-State
TGT 6988.59 < 70 >
|- HWP
Min 6988.59 < 70 >
Max 6988.59 < 70 >
TGT AUTO < 0 >
|- Turbo Boost [ UNLOCK]
1C 5790.55 < 58 >
2C 5790.55 < 58 >
3C 5491.04 < 55 >
4C 5491.04 < 55 >
5C 5491.04 < 55 >
6C 5491.04 < 55 >
7C 5491.04 < 55 >
8C 5491.04 < 55 >
|- Hybrid [ UNLOCK]
1C 4292.97 < 43 >
|- Uncore [ UNLOCK]
Min 798.69 < 8 >
Max 4991.82 < 50 >
|- TDP Level [ 0:3 ]
|- Programmable [ UNLOCK]
|- Configuration [ LOCK]
|- Turbo Activation [ UNLOCK]
Nominal 2995.11 [ 30 ]
Turbo AUTO < 0 >
Instruction Set Extensions
|- 3DNow!/Ext [N/N] ADX [Y] AES [Y] AVX/AVX2 [Y/Y]
|- AVX512-F [N] AVX512-DQ [N] AVX512-IFMA [N] AVX512-PF [N]
|- AVX512-ER [N] AVX512-CD [N] AVX512-BW [N] AVX512-VL [N]
|- AVX512-VBMI [N] AVX512-VBMI2 [N] AVX512-VNNI [N] AVX512-ALG [N]
|- AVX512-VPOP [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N]
|- AVX512-BF16 [N] AVX-VNNI-VEX [Y] MOVDIRI [Y] MOVDIR64B [Y]
|- BMI1/BMI2 [Y/Y] CLWB [Y] CLFLUSH [Y] CLFLUSH-OPT [Y]
|- CLAC-STAC [Y] CMOV [Y] CMPXCHG8B [Y] CMPXCHG16B [Y]
|- F16C [Y] FPU [Y] FXSR [Y] LAHF-SAHF [Y]
|- ENQCMD [N] GFNI [Y] OSPKE [Y] WAITPKG [Y]
|- MMX/Ext [Y/N] MON/MWAITX [Y/N] MOVBE [Y] PCLMULQDQ [Y]
|- POPCNT [Y] RDRAND [Y] RDSEED [Y] RDTSCP [Y]
|- SEP [Y] SHA [Y] SSE [Y] SSE2 [Y]
|- SSE3 [Y] SSSE3 [Y] SSE4.1/4A [Y/N] SSE4.2 [Y]
|- SERIALIZE [Y] SYSCALL [Y] RDPID [Y] SGX [N]
|- VAES [Y] VPCLMULQDQ [Y] PREFETCH/W [Y] LZCNT [Y]
Features
|- 1 GB Pages Support 1GB-PAGES [Capable]
|- Advanced Configuration & Power Interface ACPI [Capable]
|- Advanced Programmable Interrupt Controller APIC [Capable]
|- APIC Timer Invariance ARAT [Capable]
|- Core Multi-Processing CMP Legacy [Missing]
|- L1 Data Cache Context ID CNXT-ID [Missing]
|- Direct Cache Access DCA [Missing]
|- Debugging Extension DE [Capable]
|- Debug Store & Precise Event Based Sampling DS, PEBS [Capable]
|- CPL Qualified Debug Store DS-CPL [Capable]
|- 64-Bit Debug Store DTES64 [Capable]
|- Fast Short REP CMPSB FSRC [Missing]
|- Fast Short REP MOVSB FSRM [Capable]
|- Fast Short REP STOSB FSRS [Capable]
|- Fast Zero-length REP MOVSB FZRM [Missing]
|- Fast-String Operation ERMS [Capable]
|- Fused Multiply Add FMA | FMA4 [Capable]
|- Hardware Feedback Interface HFI [Capable]
|- Hardware Lock Elision HLE [Missing]
|- History Reset HRESET [Capable]
|- Hybrid part processor HYBRID [Capable]
|- Instruction Based Sampling IBS [Missing]
|- Instruction INVPCID INVPCID [Capable]
|- Long Mode 64 bits IA64 | LM [Capable]
|- Linear Address Masking LAM [Missing]
|- LightWeight Profiling LWP [Missing]
|- Machine-Check Architecture MCA [Capable]
|- Memory Protection Extensions MPX [Missing]
|- Model Specific Registers MSR [Capable]
|- Memory Type Range Registers MTRR [Capable]
|- OS-Enabled Ext. State Management OSXSAVE [Capable]
|- Physical Address Extension PAE [Capable]
|- Page Attribute Table PAT [Capable]
|- Pending Break Enable PBE [Capable]
|- Platform Configuration PCONFIG [Capable]
|- Process Context Identifiers PCID [Capable]
|- Perfmon and Debug Capability PDCM [Capable]
|- Page Global Enable PGE [Capable]
|- Page Size Extension PSE [Capable]
|- 36-bit Page Size Extension PSE36 [Capable]
|- Processor Serial Number PSN [Missing]
|- Write Data to a Processor Trace Packet PTWRITE [Capable]
|- Resource Director Technology/PQE RDT-A [Missing]
|- Resource Director Technology/PQM RDT-M [Missing]
|- Restricted Transactional Memory RTM [Missing]
|- Safer Mode Extensions SMX [Capable]
|- Self-Snoop SS [Capable]
|- Supervisor-Mode Access Prevention SMAP [Capable]
|- Supervisor-Mode Execution Prevention SMEP [Capable]
|- Thread Director TD [Capable]
|- Time Stamp Counter TSC [Invariant]
|- Time Stamp Counter Deadline TSC-DEADLINE [Capable]
|- TSX Force Abort MSR Register TSX-ABORT [Missing]
|- TSX Suspend Load Address Tracking TSX-LDTRK [Missing]
|- User-Mode Instruction Prevention UMIP [Capable]
|- Virtual Mode Extension VME [Capable]
|- Virtual Machine Extensions VMX [Capable]
|- Write Back & Do Not Invalidate Cache WBNOINVD [Missing]
|- Extended xAPIC Support x2APIC [ xAPIC]
|- Execution Disable Bit Support XD-Bit [Capable]
|- XSAVE/XSTOR States XSAVE [Capable]
|- xTPR Update Control xTPR [Capable]
Mitigation mechanisms
|- Indirect Branch Restricted Speculation IBRS [Capable]
|- Indirect Branch Prediction Barrier IBPB [Capable]
|- Single Thread Indirect Branch Predictor STIBP [Capable]
|- Speculative Store Bypass Disable SSBD [Capable]
|- Writeback & invalidate the L1 data cache L1D-FLUSH [Capable]
|- Hypervisor - No flush L1D on VM entry L1DFL_VMENTRY_NO [ Enable]
|- Arch - Buffer Overwriting MD-CLEAR [Capable]
|- Arch - No Rogue Data Cache Load RDCL_NO [ Enable]
|- Arch - Enhanced IBRS IBRS_ALL [ Enable]
|- Arch - Return Stack Buffer Alternate RSBA [Capable]
|- Arch - No Speculative Store Bypass SSB_NO [Capable]
|- Arch - No Microarchitectural Data Sampling MDS_NO [ Enable]
|- Arch - No TSX Asynchronous Abort TAA_NO [ Enable]
|- Arch - No Page Size Change MCE PSCHANGE_MC_NO [ Enable]
|- Arch - STLB QoS STLB [ Enable]
|- Arch - Functional Safety Island FuSa [ Enable]
|- Arch - RSM in CPL0 only RSM [ Enable]
|- Arch - Split Locked Access Exception SPLA [ Enable]
|- Arch - Snoop Filter QoS Mask SNOOP_FILTER [ Enable]
|- Arch - No Fast Predictive Store Forwarding PSFD [Capable]
|- Arch - Data Operand Independent Timing Mode DOITM [Capable]
|- Arch - Not affected by SBDR or SSDP SBDR_SSDP_NO [ Enable]
|- Arch - No Fill Buffer Stale Data Propagator FBSDP_NO [ Enable]
|- Arch - No Primary Stale Data Propagator PSDP_NO [ Enable]
|- Arch - Overwrite Fill Buffer values FB_CLEAR [Capable]
|- Arch - Special Register Buffer Data Sampling SRBDS [ Unable]
|- RDRAND and RDSEED mitigation RNGDS [ Unable]
|- Restricted Transactional Memory RTM [ Unable]
|- Verify Segment for Writing instruction VERW [ Unable]
|- Arch - Restricted RSB Alternate RRSBA [ Enable]
|- Arch - No Branch Target Injection BHI_NO [Capable]
|- Arch - Legacy xAPIC Disable XAPIC_DIS [ Unable]
|- Arch - No Post-Barrier Return Stack Buffer PBRSB_NO [Capable]
|- Arch - IPRED disabled for CPL3 IPRED_DIS_U [Capable]
|- Arch - IPRED disabled for CPL0/1/2 IPRED_DIS_S [Capable]
|- Arch - RRSBA disabled for CPL3 RRSBA_DIS_U [Capable]
|- Arch - RRSBA disabled for CPL0/1/2 RRSBA_DIS_S [Capable]
|- Arch - BHI disabled for CPL0/1/2 BHI_DIS_S [Capable]
|- No MXCSR Configuration Dependent Timing MCDT_NO [ Unable]
Security Features
|- CPUID Key Locker KL [Capable]
|- AES Key Locker instructions AESKLE [Missing]
|- AES Wide Key Locker instructions WIDE_KL [Capable]
|- Software Guard SGX1 Extensions SGX1 [Missing]
|- Software Guard SGX2 Extensions SGX2 [Missing]
Technologies
|- Data Cache Unit
|- L1 Prefetcher L1 HW <OFF>
|- L1 IP Prefetcher L1 HW IP < ON>
|- L2 Prefetcher L2 HW < ON>
|- L2 Line Prefetcher L2 HW CL < ON>
|- System Management Mode SMM-Dual [ ON]
|- Hyper-Threading HTT [ ON]
|- SpeedStep EIST < ON>
|- Dynamic Acceleration IDA [ ON]
|- Turbo Boost Max 3.0 TURBO < ON>
|- Energy Efficiency Optimization EEO <OFF>
|- Race To Halt Optimization R2H <OFF>
|- Watchdog Timer TCO <OFF>
|- Virtualization VMX [ ON]
|- I/O MMU VT-d [ ON]
|- Version [ 4.0]
|- Hypervisor [OFF]
|- Vendor ID [ N/A]
Performance Monitoring
|- Version PM [ 5]
|- Counters: General Fixed
| { 6, 0, 0 } x 48 bits 3 x 48 bits
|- Enhanced Halt State C1E < ON>
|- C1 Auto Demotion C1A < ON>
|- C3 Auto Demotion C3A <OFF>
|- C1 UnDemotion C1U < ON>
|- C3 UnDemotion C3U <OFF>
|- C6 Core Demotion CC6 <OFF>
|- C6 Module Demotion MC6 <OFF>
|- Legacy Frequency ID control FID [OFF]
|- Legacy Voltage ID control VID [OFF]
|- P-State Hardware Coordination Feedback MPERF/APERF [ ON]
|- Hardware Duty Cycling HDC [OFF]
|- Package C-States
|- Configuration Control CONFIG [ UNLOCK]
|- Lowest C-State LIMIT < C0>
|- I/O MWAIT Redirection IOMWAIT <Disable>
|- Max C-State Inclusion RANGE < C8>
|- Core C-States
|- C-States Base Address BAR [ 0x1814]
|- ACPI Processor C-States _CST [ 3]
|- MONITOR/MWAIT
|- State index: #0 #1 #2 #3 #4 #5 #6 #7
|- Sub C-State: 0 2 0 2 0 1 0 1
|- Core Cycles [Capable]
|- Instructions Retired [Capable]
|- Reference Cycles [Capable]
|- Last Level Cache References [Capable]
|- Last Level Cache Misses [Capable]
|- Branch Instructions Retired [Capable]
|- Branch Mispredicts Retired [Capable]
|- Top-down slots Counter [Capable]
|- Processor Performance Control _PCT [ Enable]
|- Performance Supported States _PSS [ 0]
|- Performance Present Capabilities _PPC [ 0]
Power, Current & Thermal
|- Temperature Offset:Junction TjMax < 0:100 C>
|- Clock Modulation ODCM <Disable>
|- DutyCycle [ 0.00%]
|- Power Management PWR MGMT [ LOCK]
|- Energy Policy Bias Hint [ 0]
|- Energy Policy HWP EPP < 0>
|- Digital Thermal Sensor DTS [Capable]
|- Power Limit Notification PLN [Capable]
|- Package Thermal Management PTM [Capable]
|- Thermal Monitor 1 TM1 [ Enable]
|- Thermal Monitor 2 TM2 [Capable]
|- Thermal Design Power TDP [ 125 W]
|- Minimum Power Min [Missing]
|- Maximum Power Max [Missing]
|- Thermal Design Power Package < Enable>
|- Power Limit PL1 < 4095 W>
|- Time Window TW1 < 8 s>
|- Power Limit PL2 < 4095 W>
|- Time Window TW2 < 2 ms>
|- Thermal Design Power Core <Disable>
|- Power Limit PL1 < 0 W>
|- Time Window TW1 < 976 us>
|- Thermal Design Power Uncore <Disable>
|- Power Limit PL1 < 0 W>
|- Time Window TW1 < 976 us>
|- Thermal Design Power DRAM [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 976 us]
|- Thermal Design Power Platform <Disable>
|- Power Limit PL1 < 125 W>
|- Time Window TW1 < 1 s>
|- Power Limit PL2 < 0 W>
|- Time Window TW2 < 976 us>
|- Electrical Design Current EDC [Missing]
|- Thermal Design Current TDC [Missing]
|- Core Thermal Point
|- DTS Threshold #1 Threshold [Missing]
|- DTS Threshold #2 Threshold [Missing]
|- Package Thermal Point
|- DTS Threshold #1 Threshold [Missing]
|- DTS Threshold #2 Threshold [Missing]
|- Units
|- Power watt [ 0.125000000]
|- Energy joule [ 0.000061035]
|- Window second [ 0.000976562]
CPU Pkg Apic Core/Thread Caches (w)rite-Back (i)nclusive
# ID ID Hybrid ID/ID L1-Inst Way L1-Data Way L2 Way L3 Way
000:BSP 0 P 1 0 0 32768 8 49152 12 2097152 16 37748736 12
001: 0 1 P 1 0 1 32768 8 49152 12 2097152 16 37748736 12
002: 0 8 P 1 4 0 32768 8 49152 12 2097152 16 37748736 12
003: 0 9 P 1 4 1 32768 8 49152 12 2097152 16 37748736 12
004: 0 16 P 1 8 0 32768 8 49152 12 2097152 16 37748736 12
005: 0 17 P 1 8 1 32768 8 49152 12 2097152 16 37748736 12
006: 0 24 P 1 12 0 32768 8 49152 12 2097152 16 37748736 12
007: 0 25 P 1 12 1 32768 8 49152 12 2097152 16 37748736 12
008: 0 32 P 1 16 0 32768 8 49152 12 2097152 16 37748736 12
009: 0 33 P 1 16 1 32768 8 49152 12 2097152 16 37748736 12
010: 0 40 P 1 20 0 32768 8 49152 12 2097152 16 37748736 12
011: 0 41 P 1 20 1 32768 8 49152 12 2097152 16 37748736 12
012: 0 48 P 1 24 0 32768 8 49152 12 2097152 16 37748736 12
013: 0 49 P 1 24 1 32768 8 49152 12 2097152 16 37748736 12
014: 0 56 P 1 28 0 32768 8 49152 12 2097152 16 37748736 12
015: 0 57 P 1 28 1 32768 8 49152 12 2097152 16 37748736 12
016: 0 64 E 1 32 0 65536 8 32768 8 4194304 16 37748736 12
017: 0 66 E 1 33 0 65536 8 32768 8 4194304 16 37748736 12
018: 0 68 E 1 34 0 65536 8 32768 8 4194304 16 37748736 12
019: 0 70 E 1 35 0 65536 8 32768 8 4194304 16 37748736 12
020: 0 72 E 1 36 0 65536 8 32768 8 4194304 16 37748736 12
021: 0 74 E 1 37 0 65536 8 32768 8 4194304 16 37748736 12
022: 0 76 E 1 38 0 65536 8 32768 8 4194304 16 37748736 12
023: 0 78 E 1 39 0 65536 8 32768 8 4194304 16 37748736 12
024: 0 80 E 1 40 0 65536 8 32768 8 4194304 16 37748736 12
025: 0 82 E 1 41 0 65536 8 32768 8 4194304 16 37748736 12
026: 0 84 E 1 42 0 65536 8 32768 8 4194304 16 37748736 12
027: 0 86 E 1 43 0 65536 8 32768 8 4194304 16 37748736 12
028: 0 88 E 1 44 0 65536 8 32768 8 4194304 16 37748736 12
029: 0 90 E 1 45 0 65536 8 32768 8 4194304 16 37748736 12
030: 0 92 E 1 46 0 65536 8 32768 8 4194304 16 37748736 12
031: 0 94 E 1 47 0 65536 8 32768 8 4194304 16 37748736 12
[ 0] American Megatrends International, LLC.
[ 1] F23a
[ 2] 01/04/2023
[ 3] Gigabyte Technology Co., Ltd.
[ 4] Z690 AORUS XTREME
[ 5] -CF
[ 6] D---u---s---n-
[ 7] Default string
[ 8] Z690 MB
[ 9] Gigabyte Technology Co., Ltd.
[10] Z690 AORUS XTREME
[11] x.x
[12] D---u---s---n-
[13] Number Of Devices:4\Maximum Capacity:134217728 kilobytes
[14]
[15] Controller0-ChannelA-DIMM1\BANK 0
[16]
[17] Controller1-ChannelA-DIMM1\BANK 0
[18]
[19] G Skill Intl
[20]
[21] G Skill Intl
[22]
[23] F5-7800J3646H16G
[24]
[25] F5-7800J3646H16G
Intel Z690 [7A84]
Controller #0 Dual Channel
Bus Rate 4500 MHz Bus Speed 4492 MHz DDR5 Speed 3494 MHz
Cha CL RCD RP RAS RRDs RRDl FAW WR RTPr WTPr CWL CKE CMD GEAR
#0 32 40 40 28 6 8 16 10 10 40 26 4 1T 2
#1 32 40 40 28 6 8 16 10 10 40 26 4 1T 2
sgRR dgRR drRR ddRR sgRW dgRW drRW ddRW sgWR dgWR drWR ddWR
#0 14 8 16 18 18 18 22 24 76 46 10 10
#1 14 8 16 18 18 18 22 24 76 46 10 10
sgWW dgWW drWW ddWW REFI RFC XS XP CPDED ECC
#0 36 8 14 14 111111 400 1023 4 18 0
#1 36 8 14 14 111111 400 1023 4 18 0
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 16 1 131072 1024 8192 F5-7800J3646H16G
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 16 1 131072 1024 8192 F5-7800J3646H16G
Controller #1 Disabled
CPU Freq(MHz) VID Vcore TMP(C) Accumulator Energy(J) Power(W)
000 19.01 0 0.0000 30 000000000000000000 0.000000000 0.000000000
001 1.03 0 0.0000 30 000000000000000000 0.000000000 0.000000000
002 2.16 0 0.0000 28 000000000000000000 0.000000000 0.000000000
003 1.01 0 0.0000 28 000000000000000000 0.000000000 0.000000000
004 1.86 0 0.0000 28 000000000000000000 0.000000000 0.000000000
005 1.25 0 0.0000 28 000000000000000000 0.000000000 0.000000000
006 7.45 0 0.0000 27 000000000000000000 0.000000000 0.000000000
007 0.94 0 0.0000 27 000000000000000000 0.000000000 0.000000000
008 6.00 0 0.0000 30 000000000000000000 0.000000000 0.000000000
009 0.56 0 0.0000 30 000000000000000000 0.000000000 0.000000000
010 13.55 10944 1.3359 28 000000000000000000 0.000000000 0.000000000
011 0.65 0 0.0000 28 000000000000000000 0.000000000 0.000000000
012 8.84 0 0.0000 30 000000000000000000 0.000000000 0.000000000
013 0.54 0 0.0000 30 000000000000000000 0.000000000 0.000000000
014 18.13 0 0.0000 27 000000000000000000 0.000000000 0.000000000
015 1.93 0 0.0000 27 000000000000000000 0.000000000 0.000000000
016 3.43 0 0.0000 30 000000000000000000 0.000000000 0.000000000
017 2.23 0 0.0000 30 000000000000000000 0.000000000 0.000000000
018 0.92 0 0.0000 30 000000000000000000 0.000000000 0.000000000
019 0.76 0 0.0000 30 000000000000000000 0.000000000 0.000000000
020 1.08 0 0.0000 30 000000000000000000 0.000000000 0.000000000
021 1.34 0 0.0000 30 000000000000000000 0.000000000 0.000000000
022 0.67 0 0.0000 30 000000000000000000 0.000000000 0.000000000
023 0.43 0 0.0000 30 000000000000000000 0.000000000 0.000000000
024 1.04 0 0.0000 31 000000000000000000 0.000000000 0.000000000
025 14.86 0 0.0000 31 000000000000000000 0.000000000 0.000000000
026 87.28 0 0.0000 31 000000000000000000 0.000000000 0.000000000
027 0.62 0 0.0000 31 000000000000000000 0.000000000 0.000000000
028 0.48 0 0.0000 32 000000000000000000 0.000000000 0.000000000
029 2.01 0 0.0000 32 000000000000000000 0.000000000 0.000000000
030 0.66 0 0.0000 32 000000000000000000 0.000000000 0.000000000
031 1.54 10780 0.0000 32 000000000000000000 0.000000000 0.000000000
Package[0] Cores Uncore Memory Platform
Energy(J): 8.445556641 6.971984863 0.000000000 0.000000000 0.000000000
Power(W) : 8.445556641 6.971984863 0.000000000 0.000000000 0.000000000
Thank you.
Memory Size
is still not OK yet. Will try other bits.
Uncore range change is btw available in branch.
Does your BIOS say "Dual" or "Quad" channels ? If you have some BIOS screenshots about IMC, DIMM, Timings and so on, those will help, because I don't know what I'm supposed to decode ?
From manual, Memory Channels Timing screens are those I would like to see, plz.
Another request is to change the Voltage scope to [Core] or [SMT] and see if Vcore gets resolved for both Pcore and Ecore ?
For example, based on your previous output, two Vcore matter:
010 13.55 10944 1.3359 28 000000000000000000 0.000000000 0.000000000
031 1.54 10780 0.0000 32 000000000000000000 0.000000000 0.000000000
Here are all setting screens I could find + cpu-z output:
Set to Core:
Thank you.
So CPU-Z is showing it as Quad 32-bits channels, like for Zen, but Intel differs from AMD in the number of controllers associated: for two DIMM sticks, 2 controllers for Intel vs 4 controllers for AMD
Somehow CoreFreq does not report tRC
. I've to check why it misses.
Hello,
Using latest commits, you will get:
tRCD_WR
in the JSON export may show up~tRC
is not found among datasheetsCan you also switch to Experimental mode in Settings
window and enable ODCM
in Power, Current & Thermal
window ?
|- Clock Modulation ODCM <Disable>
|- DutyCycle [ 0.00%]
Next you set for example a DutyCycle
at 50%
; press !
to toggle the Absolute frequency
and look for reduction effects.
REFI is now broken max value is 262143 I use 111111:
Duty Cycle 50%:
Small correction to the duty cycle is applied, just not displayed correctly.
Thank you for your answers
I will thus make ODCM
fully available on RPL
I wonder if tREFI
is only broken because of space missing on UI ?
Could you also refresh from develop
and export CLI in json ?
corefreq-cli -j
I am interested by the IMC timings part like it has been tested on Alder Lake:
{
"B2B": 2,
"CMD_Rate": 1,
"ECC": 0,
"tCL": 32,
"tCWL": 26,
"tFAW": 16,
"tRAS": 28,
"tRCD_R": 40,
"tRCD_W": 40,
"tRFC": 400,
"tRP": 40,
"tRRD": 6,
"tRTPr": 10,
"tWR": 10,
"tWTPr": 40,
"tddRdTRd": 18,
"tddRdTWr": 14,
"tddWrTRd": 8,
"tddWrTWr": 16,
"tdrRdTRd": 18,
"tdrRdTWr": 24,
"tdrWrTRd": 46,
"tdrWrTWr": 10,
"tsrRdTRd": 18,
"tsrRdTWr": 22,
"tsrWrTRd": 76,
"tsrWrTWr": 10
}
Yes !
tRCD_W
confirmed on RPL + DDR5
But not on ADL + DDR4
REFI is now broken max value is 262143 I use 111111:
Space is indeed missing: only 5 digits. However I can split value in 2 cells ...
You can now pull the last commit to read tREFI
in full value.
Available for Intel DDR4/DDR5
Yes, everything is working. Thank you for your help.
Is the possibility to set memory timings planed?
Is the possibility to set memory timings planed?
I would jump on such feature if allowed to do it but datasheets I have read so far say no, read-only.
Set to Core:
Could you try this view again (using the very last commit) to see if the SA (System Agent) VID is now converting into voltage ?
If you look at my BIOS screenshots, there is a setting "Realtime Memory Timing" This allows to write access, but I don't know if it uses the same registers.
SA voltage is the Voltage which is set in BIOS.
If you look at my BIOS screenshots, there is a setting "Realtime Memory Timing" This allows to write access, but I don't know if it uses the same registers.
And I wonder if it talks about SPD data as mentioned here : I have no clue of such Registers.
Do you know if XTU or other low-level Windows software are capable to alter IMC timings ?
Concerning the IMC Registers I'm using in CoreFreq: in the past I have forced writing them through MMIO mapping and it immediately crashed kernel.
Allok
Hello, I forgot to activate the Uncore PMU
Can you please pull and build from latest develop
commits then post corefreq-cli -g 1
or screenshot the Package cycles
view.
The UNCORE
value should not be zero and within the Min, Max Uncore frequencies as shown in Processor
window.
Small addition, the min value doesn't get applied. I have to check if this maybe is BIOS related, uncore always moves around 4.2Ghz - 4.5Ghz
Small addition, the min value doesn't get applied. I have to check if this maybe is BIOS related, uncore always moves around 4.2Ghz - 4.5Ghz
Very odd because you have a K processor. I have been able to alter Min ratio from a Mobile Tiger Lake Can you show screenshots before and after ? Those Uncore Min Max ratios are MSR registers; you should try first to write them and read afterward for effect.
@justanerd
This MSR https://github.com/cyring/CoreFreq/blob/b7038862f0ca08e2a9a405173567a48b2ddea715/intel_reg.h#L146
This bits specification https://github.com/cyring/CoreFreq/blob/b7038862f0ca08e2a9a405173567a48b2ddea715/intel_reg.h#L1509
Presuming 08
as Min and 50 (0x32)
as Max initial ratios, enter the following commands.
## Read initial ratios
rdmsr -ax 0x00000620
0x0832
...
0x0832
## Write Min ratio to 0x32
wrmsr -a 0x00000620 0x3232
## Read register again to check if value is taken into account
rdmsr -ax 0x00000620
0x3232 ## is OK
I tested a bit further as long as the E-Cores are not loaded the min/max get applied if all cores are loaded the BIOS seems to have a hard-coded limit of 4,5Ghz. I can override this in the BIOS, but its pointless performance doesn't increase, but power usage does. So with CoreFreq everything is right.
I tested a bit further as long as the E-Cores are not loaded the min/max get applied if all cores are loaded the BIOS seems to have a hard-coded limit of 4,5Ghz. I can override this in the BIOS, but its pointless performance doesn't increase, but power usage does. So with CoreFreq everything is right.
Thank you for your return. I did not push ratio so high; it's worth to test the TGL Uncore for its max limit.
Hello,
Using latest master
branch, can you please post a screenshot of the Memory Controller ?
Since your last test, developments have impacted the Bus Rate and Speed, DRAM Speed, Controllers topology.
@testjkiio
Thank you for your IMC data. It looks coherent with what I can google about F5-7800J3646H16G
.
corefreq-cli -s -n -m -n -B -n -M -n -C 1