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cyring / CoreFreq

CoreFreq : CPU monitoring and tuning software designed for 64-bit processors.
https://www.cyring.fr
GNU General Public License v2.0
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Goldmont Plus memory controller not read (regression?) #442

Closed Chlorophytus closed 1 year ago

Chlorophytus commented 1 year ago

On a Pentium Silver N5000 in an HP Laptop 15-dw0xxxx, the memory controller information does not show. I'm thinking it used to show, but there is either a regression that makes lookup fail, or the function has not been implemented in CoreFreq yet.

Linux 6.3.1 on openSUSE Tumbleweed, CoreFreq 1.96.1.

image

cyring commented 1 year ago

Could you tell which is the last good working version ?

https://github.com/cyring/CoreFreq/tags

cyring commented 1 year ago

https://github.com/cyring/CoreFreq/blob/a28ea7bea3cab13493c1011d28fa2d564722cd3a/corefreqk.c#L5296

Version 1.94.0 , IMC was partially implemented.

cyring commented 1 year ago

Hello, Are you ok to provide quick tests if I create a development branch ?

Fyi: last issue of developpements where IMC remained unsolved: https://github.com/cyring/CoreFreq/issues/389

Chlorophytus commented 1 year ago

Hello,

Are you ok to provide quick tests if I create a development branch ?

Fyi: last issue of developpements where IMC remained unsolved:

https://github.com/cyring/CoreFreq/issues/389

I would be fine with that.

cyring commented 1 year ago

At this post please download CoreFreq_develop.tar.gz

Decompress archive and load the driver:

make clean all
insmod ./corefreqk.ko

In your kernel log (dmesg), It should dump Registers between these two markers:

CoreFreq: ---------------- DUMP START ----------------
CoreFreq: ---------------- DUMP  STOP ----------------

Can you post them here in Markdown format. Thank you.

EDIT: Registers datasheet is available at https://www.mouser.com/pdfdocs/silver-celeron-datasheet-vol-2.pdf

Chlorophytus commented 1 year ago

@cyring In that develop code commit, line 20480 and column 12, compilation of corefreqk.c failed with "void value not ignored as it ought to be".

20480 |         rc = cpufreq_unregister_driver(&CoreFreqK.FreqDriver);
      |            ^
cyring commented 1 year ago

@cyring In that develop code commit, line 20480 and column 12, compilation of corefreqk.c failed with "void value not ignored as it ought to be".

20480 |         rc = cpufreq_unregister_driver(&CoreFreqK.FreqDriver);
      |            ^

Ok let me fix that, it's an old kernel API issue

cyring commented 1 year ago

Hello,

Can you pull the dedicated branch develop_goldmont, build, load the kernel module and provide the DUMP ?

Thank you

Chlorophytus commented 1 year ago

Hello,

Can you pull the dedicated branch develop_goldmont, build, load the kernel module and provide the DUMP ?

Thank you

[19387.546886] CoreFreq(0:-1:-1): Processor [ 06_7A] Architecture [Gemini Lake] CPU [4/4]
[19387.546962] CoreFreq: ---------------- DUMP START ----------------
[19387.546967] CoreFreq: 0x00001000   0x00001200   0x00001400   0x00001600
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[19387.546974] CoreFreq: 0x00001004   0x00001204   0x00001404   0x00001604
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[19387.546979] CoreFreq: 0x00001008   0x00001208   0x00001408   0x00001608
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[19387.546985] CoreFreq: 0x0000100c   0x0000120c   0x0000140c   0x0000160c
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[19387.546991] CoreFreq: 0x00001010   0x00001210   0x00001410   0x00001610
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[19387.546997] CoreFreq: 0x00001014   0x00001214   0x00001414   0x00001614
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[19387.547002] CoreFreq: 0x00001018   0x00001218   0x00001418   0x00001618
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[19387.547008] CoreFreq: 0x0000101c   0x0000121c   0x0000141c   0x0000161c
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[19387.547014] CoreFreq: 0x00001020   0x00001220   0x00001420   0x00001620
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[19387.547019] CoreFreq: 0x00001024   0x00001224   0x00001424   0x00001624
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[19387.547025] CoreFreq: 0x00001028   0x00001228   0x00001428   0x00001628
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[19387.547030] CoreFreq: 0x0000102c   0x0000122c   0x0000142c   0x0000162c
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[19387.547036] CoreFreq: 0x00001030   0x00001230   0x00001430   0x00001630
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[19387.547041] CoreFreq: 0x00001034   0x00001234   0x00001434   0x00001634
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[19387.547047] CoreFreq: 0x00001038   0x00001238   0x00001438   0x00001638
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[19387.547053] CoreFreq: 0x0000103c   0x0000123c   0x0000143c   0x0000163c
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[19387.547058] CoreFreq: 0x00001040   0x00001240   0x00001440   0x00001640
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[19387.547064] CoreFreq: 0x00001044   0x00001244   0x00001444   0x00001644
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[19387.547069] CoreFreq: 0x00001048   0x00001248   0x00001448   0x00001648
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[19387.547075] CoreFreq: 0x0000104c   0x0000124c   0x0000144c   0x0000164c
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[19387.547077] CoreFreq: ---------------- DUMP  STOP ----------------
cyring commented 1 year ago

Page 161 "Host Memory Mapped Configuration Space (MCHBAR) Registers" of datasheet vol 2. This is where I'm stuck, registers values are 0xffffffff which means no Register!

cyring commented 1 year ago

@Chlorophytus Hello,

Please pull and dump using new commit 88edaf8bf9971f94891742aac3d27570d52c55b4 in develop_goldmont branch.

Chlorophytus commented 1 year ago

@Chlorophytus Hello,

Please pull and dump using new commit 88edaf8 in develop_goldmont branch.

[24162.559087] CoreFreq(1:-1:-1): Processor [ 06_7A] Architecture [Gemini Lake] CPU [4/4]
[24162.559165] CoreFreq: ---------------- DUMP START ----------------
[24162.559170] CoreFreq: 0x00001000   0x00001200   0x00001400   0x00001600
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[24162.559177] CoreFreq: 0x00001004   0x00001204   0x00001404   0x00001604
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[24162.559182] CoreFreq: 0x00001008   0x00001208   0x00001408   0x00001608
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[24162.559188] CoreFreq: 0x0000100c   0x0000120c   0x0000140c   0x0000160c
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[24162.559194] CoreFreq: 0x00001010   0x00001210   0x00001410   0x00001610
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[24162.559199] CoreFreq: 0x00001014   0x00001214   0x00001414   0x00001614
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[24162.559205] CoreFreq: 0x00001018   0x00001218   0x00001418   0x00001618
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[24162.559211] CoreFreq: 0x0000101c   0x0000121c   0x0000141c   0x0000161c
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[24162.559216] CoreFreq: 0x00001020   0x00001220   0x00001420   0x00001620
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[24162.559222] CoreFreq: 0x00001024   0x00001224   0x00001424   0x00001624
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[24162.559227] CoreFreq: 0x00001028   0x00001228   0x00001428   0x00001628
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[24162.559233] CoreFreq: 0x0000102c   0x0000122c   0x0000142c   0x0000162c
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[24162.559239] CoreFreq: 0x00001030   0x00001230   0x00001430   0x00001630
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[24162.559244] CoreFreq: 0x00001034   0x00001234   0x00001434   0x00001634
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[24162.559250] CoreFreq: 0x00001038   0x00001238   0x00001438   0x00001638
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[24162.559255] CoreFreq: 0x0000103c   0x0000123c   0x0000143c   0x0000163c
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[24162.559261] CoreFreq: 0x00001040   0x00001240   0x00001440   0x00001640
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[24162.559267] CoreFreq: 0x00001044   0x00001244   0x00001444   0x00001644
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[24162.559272] CoreFreq: 0x00001048   0x00001248   0x00001448   0x00001648
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[24162.559278] CoreFreq: 0x0000104c   0x0000124c   0x0000144c   0x0000164c
                        [0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[24162.559280] CoreFreq: ---------------- DUMP  STOP ----------------
cyring commented 1 year ago

(Desperately) I'll attempts to decode the IMC as the previous method from Airmont, Silvermont SoC. Please pull and dump from commit 5006a68fe42780c44e708defc4b61e0c0f4a525b "[Intel][GDM+] Attempts to decode the IMC as SoC MCR"

Chlorophytus commented 1 year ago

(Desperately) I'll attempts to decode the IMC as the previous method from Airmont, Silvermont SoC. Please pull and dump from commit 5006a68 "[Intel][GDM+] Attempts to decode the IMC as SoC MCR"

[32070.390856] CoreFreq(3:-1:-1): Processor [ 06_7A] Architecture [Gemini Lake] CPU [4/4]
[32070.390898] CoreFreq: ---------------- DUMP START ----------------
[32070.390899] CoreFreq: DRP[0x00000000]
[32070.390900] CoreFreq: DTR0[0x00000000]
[32070.390901] CoreFreq: DTR1[0x00000000]
[32070.390902] CoreFreq: DTR2[0x00000000]
[32070.390903] CoreFreq: DTR3[0x00000000]
[32070.390904] CoreFreq: DRFC[0x00000000]
[32070.390905] CoreFreq: DRMC[0x00000000]
[32070.390906] CoreFreq: BIOS_CFG[0x00000000]
[32070.390906] CoreFreq: ---------------- DUMP  STOP ----------------

@cyring If this is a bad reading, could this be due to a problematic UEFI?

cyring commented 1 year ago

If this is a bad reading, could this be due to a problematic UEFI?

It was the same behavior in the previous issue, and I remember it was a different PC platform but for the same processor model and architecture. I won't blame the UEFI. Perhaps the device DID, I'm trying to remap in kernel space, is locked but I've not found any unlock bit in the datasheet. Maybe your UEFI has an option to hide or unlock such access ?

To sum up :

I'm lost with that IMC. Are you really able to read it from other software ? Not the DIMM spd but the IMC registers like current DRAM timings ?

Chlorophytus commented 1 year ago

If this is a bad reading, could this be due to a problematic UEFI?

It was the same behavior in the previous issue, and I remember it was a different PC platform but for the same processor model and architecture.

I won't blame the UEFI.

Perhaps the device DID, I'm trying to remap in kernel space, is locked but I've not found any unlock bit in the datasheet.

Maybe your UEFI has an option to hide or unlock such access ?

To sum up :

  • Last branch commit is based on the IMC decoder from Airmont & Silvermont architectures. We have no results with the N5000 which is a Goldmont+

  • First commit is especially made for GDM+.

Registers access is a memory base address remap method. A method which works with most architectures handled by CoreFreq whatever the base address is.

I'm lost with that IMC. Are you really able to read it from other software ? Not the DIMM spd but the IMC registers like current DRAM timings ?

I haven't tried other software to get timings

cyring commented 1 year ago

I haven't tried other software to get timings

@Chlorophytus: I would suggest you give a try to memtest86plus Last week have been committed code to decode various IMCs. It's worth to build and run from latest source code. If it successfully reads Timings, please take a picture.

Chlorophytus commented 1 year ago

I haven't tried other software to get timings

@Chlorophytus:

I would suggest you give a try to memtest86plus

Last week have been committed code to decode various IMCs.

It's worth to build and run from latest source code.

If it successfully reads Timings, please take a picture.

@cyring With latest MemTest86+ from git image

cyring commented 1 year ago

Reading code I don't see a reference to a Goldmont Plus IMC decoder. I don't even find the cpuid of the Processor. My understanding is that the screen shows Timings from the DIMM SPD.

EDIT: data look sourced from the smbus controller in lookup table intel_ich5_dids , values assigned at theses lines

cyring commented 1 year ago

Commit 3fc5acd534bee4170262dc82605e1e6076919dd1 will scan for up to 8 controllers. Indeed, within other architectures, I found that controller #0 is enabled but not necessary activated. In your kernel log, you will get a bunch of traces, surrounded by the following markers:

CoreFreq: ---------------- BAR START ----------------
CoreFreq: ---------------- MMIO START[12] -------------
CoreFreq: ---------------- MMIO  STOP ----------------
CoreFreq: ---------------- BAR STOP[12345678] -------

Thank you for your test.

Chlorophytus commented 1 year ago

Commit 3fc5acd will scan for up to 8 controllers. Indeed, within other architectures, I found that controller #0 is enabled but not necessary activated. In your kernel log, you will get a bunch of traces, surrounded by the following markers:

CoreFreq: ---------------- BAR START ----------------
CoreFreq: ---------------- MMIO START[12] -------------
CoreFreq: ---------------- MMIO  STOP ----------------
CoreFreq: ---------------- BAR STOP[12345678] -------

Thank you for your test.

@cyring 

[  227.070827] CoreFreq(3:-1:-1): Processor [ 06_7A] Architecture [Gemini Lake] CPU [4/4]
[  227.070878] CoreFreq: ---------------- BAR START ----------------
[  227.070879] CoreFreq: BDF[0:0:0] + 0x48 MCHBAR[0x00000000fed10001] Enable[1]
[  227.070917] CoreFreq: ---------------- MMIO START[ 0] -------------
[  227.070918] CoreFreq: Offset 000000003a85621f[0xffffffff]
[  227.070921] CoreFreq: ---------------- MMIO  STOP ----------------
[  227.070927] CoreFreq: ---------------- BAR STOP[       0] -------
[  227.070930] CoreFreq: ---------------- BAR START ----------------
[  227.070931] CoreFreq: BDF[0:0:0] + 0x48 MCHBAR[0x00000000fed10001] Enable[1]
[  227.070941] resource: resource sanity check: requesting [mem 0x00000000fed18000-0x00000000fed1ffff], which spans more than PCI Bus 0000:00 [mem 0xfed1c000-0xfed1cfff window]
[  227.070946] caller RouterDebug+0x142/0x190 [corefreqk] mapping multiple BARs
[  227.071020] CoreFreq: ---------------- MMIO START[ 1] -------------
[  227.071021] CoreFreq: Offset 00000000e4b822ab[0xffffffff]
[  227.071023] CoreFreq: ---------------- MMIO  STOP ----------------
[  227.071026] CoreFreq: ---------------- BAR STOP[       0] -------
[  227.071029] CoreFreq: ---------------- BAR START ----------------
[  227.071030] CoreFreq: BDF[0:0:0] + 0x48 MCHBAR[0x00000000fed10001] Enable[1]
[  227.071038] CoreFreq: ---------------- MMIO START[ 2] -------------
[  227.071039] CoreFreq: Offset 00000000a433eeae[0xffffffff]
[  227.071040] CoreFreq: ---------------- MMIO  STOP ----------------
[  227.071042] CoreFreq: ---------------- BAR STOP[       0] -------
[  227.071045] CoreFreq: ---------------- BAR START ----------------
[  227.071046] CoreFreq: BDF[0:0:0] + 0x48 MCHBAR[0x00000000fed10001] Enable[1]
[  227.071053] CoreFreq: ---------------- MMIO START[ 3] -------------
[  227.071054] CoreFreq: Offset 00000000a9b95a4a[0xffffffff]
[  227.071055] CoreFreq: ---------------- MMIO  STOP ----------------
[  227.071057] CoreFreq: ---------------- BAR STOP[       0] -------
[  227.071060] CoreFreq: ---------------- BAR START ----------------
[  227.071061] CoreFreq: BDF[0:0:0] + 0x48 MCHBAR[0x00000000fed10001] Enable[1]
[  227.071069] CoreFreq: ---------------- MMIO START[ 4] -------------
[  227.071070] CoreFreq: Offset 00000000ee51f1a5[0xffffffff]
[  227.071071] CoreFreq: ---------------- MMIO  STOP ----------------
[  227.071073] CoreFreq: ---------------- BAR STOP[       0] -------
[  227.071076] CoreFreq: ---------------- BAR START ----------------
[  227.071077] CoreFreq: BDF[0:0:0] + 0x48 MCHBAR[0x00000000fed10001] Enable[1]
[  227.071083] CoreFreq: ---------------- MMIO START[ 5] -------------
[  227.071084] CoreFreq: Offset 00000000513bbe01[0xffffffff]
[  227.071085] CoreFreq: ---------------- MMIO  STOP ----------------
[  227.071087] CoreFreq: ---------------- BAR STOP[       0] -------
[  227.071090] CoreFreq: ---------------- BAR START ----------------
[  227.071091] CoreFreq: BDF[0:0:0] + 0x48 MCHBAR[0x00000000fed10001] Enable[1]
[  227.071098] resource: resource sanity check: requesting [mem 0x00000000fed40000-0x00000000fed47fff], which spans more than MSFT0101:00 [mem 0xfed40000-0xfed44fff]
[  227.071101] caller RouterDebug+0x142/0x190 [corefreqk] mapping multiple BARs
[  227.071142] CoreFreq: ---------------- MMIO START[ 6] -------------
[  227.071143] CoreFreq: Offset 00000000127a0669[0xffffffff]
[  227.071145] CoreFreq: ---------------- MMIO  STOP ----------------
[  227.071148] CoreFreq: ---------------- BAR STOP[       0] -------
[  227.071150] CoreFreq: ---------------- BAR START ----------------
[  227.071151] CoreFreq: BDF[0:0:0] + 0x48 MCHBAR[0x00000000fed10001] Enable[1]
[  227.071163] CoreFreq: ---------------- MMIO START[ 7] -------------
[  227.071164] CoreFreq: Offset 00000000b29bb251[0xffffffff]
[  227.071165] CoreFreq: ---------------- MMIO  STOP ----------------
[  227.071167] CoreFreq: ---------------- BAR STOP[       0] -------
cyring commented 1 year ago

Can you edit and replace in function Query_GLK_IMC the offset 0x1000 by the offset of the following table.

Edit at line: https://github.com/cyring/CoreFreq/blob/3fc5acd534bee4170262dc82605e1e6076919dd1/corefreqk.c#L5350

Offset Architecture
0xd800 ADL
0x5000 TGL,RKL,SKL,BDW,HSW,IVB,SNB
Chlorophytus commented 1 year ago

Can you edit and replace in function Query_GLK_IMC the offset 0x1000 by the offset of the following table.

Edit at line:

https://github.com/cyring/CoreFreq/blob/3fc5acd534bee4170262dc82605e1e6076919dd1/corefreqk.c#L5350

Offset Architecture 0xd800 ADL 0x5000 TGL,RKL,SKL,BDW,HSW,IVB,SNB

https://gist.github.com/Chlorophytus/c4050857957dfb2475de5fe6028df290

Probing at 0xD800 results in insmod being killed and a kernel stacktrace. Probing at 0x5000 succeeds.

cyring commented 1 year ago

https://gist.github.com/Chlorophytus/c4050857957dfb2475de5fe6028df290

Probing at 0xD800 results in insmod being killed and a kernel stacktrace. Probing at 0x5000 succeeds.

[   43.216718] CoreFreq: Offset 00000000b3d6a368[0x00000000]

For once! we are not greated with a 0xffffffff but that zero would mean nothing behind.

Datasheet Document Number 336561-001 is a real pain:

  1. Introduction lists the Processor

    Throughout this document Intel® Pentium® Silver and Intel® Celeron® Processors families refer to: • Intel® Pentium® Silver N5000 • Intel® Pentium® Silver J5005 • Intel® Celeron® N4000 and N4100 • Intel® Celeron® J4105 and J4005

  2. MCHBAR is found at [B:0, D:0, F:0] + 48h with a register value of 0xFED10001

2023-05-23-193545_532x366_scrot

  1. DRAM Register address offsets are specified to start at 0x1000

2023-05-23-193327_532x397_scrot

So we are Go for the first two steps but the third one is failing on documented addresses. It's frustrating.

cyring commented 1 year ago

0xd800 offset could not be addressed because I forgot to tell you to increase the BAR size at this line

https://github.com/cyring/CoreFreq/blob/3fc5acd534bee4170262dc82605e1e6076919dd1/corefreqk.c#LL6253C47-L6253C47

from a 0x8000 to 0xe000 size

rc = RouterDebug(dev, 0x48, 64, 0xe000, Query_GLK_IMC, mc);
Chlorophytus commented 1 year ago

0xd800 offset could not be addressed because I forgot to tell you to increase the BAR size at this line

https://github.com/cyring/CoreFreq/blob/3fc5acd534bee4170262dc82605e1e6076919dd1/corefreqk.c#LL6253C47-L6253C47

from a 0x8000 to 0xe000 size

rc = RouterDebug(dev, 0x48, 64, 0xe000, Query_GLK_IMC, mc);

Doesn't do much.

[ 6636.855575] CoreFreq(3:-1:-1): Processor [ 06_7A] Architecture [Gemini Lake] CPU [4/4]
[ 6636.855601] CoreFreq: ---------------- BAR START ----------------
[ 6636.855602] CoreFreq: BDF[0:0:0] + 0x48 MCHBAR[0x00000000fed10001] Enable[1]
[ 6636.855638] resource: resource sanity check: requesting [mem 0x00000000fed10000-0x00000000fed1dfff], which spans more than PCI Bus 0000:00 [mem 0xfed1c000-0xfed1cfff window]
[ 6636.855644] caller RouterDebug+0x142/0x190 [corefreqk] mapping multiple BARs
[ 6636.855717] CoreFreq: ---------------- MMIO START[ 0] -------------
[ 6636.855718] CoreFreq: Offset 00000000556c18a0[0xffffffff]
[ 6636.855721] CoreFreq: ---------------- MMIO  STOP ----------------
[ 6636.855727] CoreFreq: ---------------- BAR STOP[       0] -------
[ 6636.855730] CoreFreq: ---------------- BAR START ----------------
[ 6636.855731] CoreFreq: BDF[0:0:0] + 0x48 MCHBAR[0x00000000fed10001] Enable[1]
[ 6636.855744] CoreFreq: ---------------- MMIO START[ 1] -------------
[ 6636.855745] CoreFreq: Offset 0000000046df2460[0xffffffff]
[ 6636.855746] CoreFreq: ---------------- MMIO  STOP ----------------
[ 6636.855749] CoreFreq: ---------------- BAR STOP[       0] -------
[ 6636.855752] CoreFreq: ---------------- BAR START ----------------
[ 6636.855752] CoreFreq: BDF[0:0:0] + 0x48 MCHBAR[0x00000000fed10001] Enable[1]
[ 6636.855761] CoreFreq: ---------------- MMIO START[ 2] -------------
[ 6636.855762] CoreFreq: Offset 00000000e5d4bd1a[0xffffffff]
[ 6636.855764] CoreFreq: ---------------- MMIO  STOP ----------------
[ 6636.855766] CoreFreq: ---------------- BAR STOP[       0] -------
[ 6636.855769] CoreFreq: ---------------- BAR START ----------------
[ 6636.855770] CoreFreq: BDF[0:0:0] + 0x48 MCHBAR[0x00000000fed10001] Enable[1]
[ 6636.855778] resource: resource sanity check: requesting [mem 0x00000000fed3a000-0x00000000fed47fff], which spans more than MSFT0101:00 [mem 0xfed40000-0xfed44fff]
[ 6636.855781] caller RouterDebug+0x142/0x190 [corefreqk] mapping multiple BARs
[ 6636.855827] CoreFreq: ---------------- MMIO START[ 3] -------------
[ 6636.855828] CoreFreq: Offset 00000000fc6ee2fc[0xffffffff]
[ 6636.855830] CoreFreq: ---------------- MMIO  STOP ----------------
[ 6636.855833] CoreFreq: ---------------- BAR STOP[       0] -------
[ 6636.855836] CoreFreq: ---------------- BAR START ----------------
[ 6636.855837] CoreFreq: BDF[0:0:0] + 0x48 MCHBAR[0x00000000fed10001] Enable[1]
[ 6636.855851] CoreFreq: ---------------- MMIO START[ 4] -------------
[ 6636.855852] CoreFreq: Offset 00000000dade2f28[0xffffffff]
[ 6636.855854] CoreFreq: ---------------- MMIO  STOP ----------------
[ 6636.855856] CoreFreq: ---------------- BAR STOP[       0] -------
[ 6636.855859] CoreFreq: ---------------- BAR START ----------------
[ 6636.855859] CoreFreq: BDF[0:0:0] + 0x48 MCHBAR[0x00000000fed10001] Enable[1]
[ 6636.855872] CoreFreq: ---------------- MMIO START[ 5] -------------
[ 6636.855873] CoreFreq: Offset 000000004552bc6b[0xffffffff]
[ 6636.855874] CoreFreq: ---------------- MMIO  STOP ----------------
[ 6636.855876] CoreFreq: ---------------- BAR STOP[       0] -------
[ 6636.855879] CoreFreq: ---------------- BAR START ----------------
[ 6636.855880] CoreFreq: BDF[0:0:0] + 0x48 MCHBAR[0x00000000fed10001] Enable[1]
[ 6636.855890] CoreFreq: ---------------- MMIO START[ 6] -------------
[ 6636.855891] CoreFreq: Offset 00000000d36df78a[0xffffffff]
[ 6636.855892] CoreFreq: ---------------- MMIO  STOP ----------------
[ 6636.855894] CoreFreq: ---------------- BAR STOP[       0] -------
[ 6636.855897] CoreFreq: ---------------- BAR START ----------------
[ 6636.855898] CoreFreq: BDF[0:0:0] + 0x48 MCHBAR[0x00000000fed10001] Enable[1]
[ 6636.855910] CoreFreq: ---------------- MMIO START[ 7] -------------
[ 6636.855911] CoreFreq: Offset 00000000d76599b1[0xffffffff]
[ 6636.855912] CoreFreq: ---------------- MMIO  STOP ----------------
[ 6636.855914] CoreFreq: ---------------- BAR STOP[       0] -------
cyring commented 1 year ago

Doesn't do much.

Thanks again. We can rollback to a BAR size of 0x8000

cyring commented 1 year ago

Looking at the channel number which has to be number 0 IMG_20230523_205858 Could you try with offset 0x1400 ?

Chlorophytus commented 1 year ago

Looking at the channel number which has to be number 0 IMG_20230523_205858 Could you try with offset 0x1400 ?

Offset 0x1400 doesn't really come up with anything.

[ 7600.160612] CoreFreq(1:-1:-1): Processor [ 06_7A] Architecture [Gemini Lake] CPU [4/4]
[ 7600.160638] CoreFreq: ---------------- BAR START ----------------
[ 7600.160640] CoreFreq: BDF[0:0:0] + 0x48 MCHBAR[0x00000000fed10001] Enable[1]
[ 7600.160678] CoreFreq: ---------------- MMIO START[ 0] -------------
[ 7600.160679] CoreFreq: Offset 00000000afabe9f5[0xffffffff]
[ 7600.160682] CoreFreq: ---------------- MMIO  STOP ----------------
[ 7600.160688] CoreFreq: ---------------- BAR STOP[       0] -------
[ 7600.160692] CoreFreq: ---------------- BAR START ----------------
[ 7600.160692] CoreFreq: BDF[0:0:0] + 0x48 MCHBAR[0x00000000fed10001] Enable[1]
[ 7600.160699] resource: resource sanity check: requesting [mem 0x00000000fed18000-0x00000000fed1ffff], which spans more than PCI Bus 0000:00 [mem 0xfed1c000-0xfed1cfff window]
[ 7600.160704] caller RouterDebug+0x142/0x190 [corefreqk] mapping multiple BARs
[ 7600.160778] CoreFreq: ---------------- MMIO START[ 1] -------------
[ 7600.160779] CoreFreq: Offset 00000000dd92c4a8[0xffffffff]
[ 7600.160781] CoreFreq: ---------------- MMIO  STOP ----------------
[ 7600.160784] CoreFreq: ---------------- BAR STOP[       0] -------
[ 7600.160787] CoreFreq: ---------------- BAR START ----------------
[ 7600.160788] CoreFreq: BDF[0:0:0] + 0x48 MCHBAR[0x00000000fed10001] Enable[1]
[ 7600.160797] CoreFreq: ---------------- MMIO START[ 2] -------------
[ 7600.160798] CoreFreq: Offset 00000000263abfa8[0xffffffff]
[ 7600.160800] CoreFreq: ---------------- MMIO  STOP ----------------
[ 7600.160803] CoreFreq: ---------------- BAR STOP[       0] -------
[ 7600.160806] CoreFreq: ---------------- BAR START ----------------
[ 7600.160806] CoreFreq: BDF[0:0:0] + 0x48 MCHBAR[0x00000000fed10001] Enable[1]
[ 7600.160813] CoreFreq: ---------------- MMIO START[ 3] -------------
[ 7600.160814] CoreFreq: Offset 000000000d5dcf46[0xffffffff]
[ 7600.160815] CoreFreq: ---------------- MMIO  STOP ----------------
[ 7600.160817] CoreFreq: ---------------- BAR STOP[       0] -------
[ 7600.160820] CoreFreq: ---------------- BAR START ----------------
[ 7600.160821] CoreFreq: BDF[0:0:0] + 0x48 MCHBAR[0x00000000fed10001] Enable[1]
[ 7600.160830] CoreFreq: ---------------- MMIO START[ 4] -------------
[ 7600.160831] CoreFreq: Offset 0000000005d5f3ad[0xffffffff]
[ 7600.160833] CoreFreq: ---------------- MMIO  STOP ----------------
[ 7600.160835] CoreFreq: ---------------- BAR STOP[       0] -------
[ 7600.160838] CoreFreq: ---------------- BAR START ----------------
[ 7600.160838] CoreFreq: BDF[0:0:0] + 0x48 MCHBAR[0x00000000fed10001] Enable[1]
[ 7600.160846] CoreFreq: ---------------- MMIO START[ 5] -------------
[ 7600.160847] CoreFreq: Offset 000000006011a121[0xffffffff]
[ 7600.160849] CoreFreq: ---------------- MMIO  STOP ----------------
[ 7600.160851] CoreFreq: ---------------- BAR STOP[       0] -------
[ 7600.160854] CoreFreq: ---------------- BAR START ----------------
[ 7600.160855] CoreFreq: BDF[0:0:0] + 0x48 MCHBAR[0x00000000fed10001] Enable[1]
[ 7600.160861] resource: resource sanity check: requesting [mem 0x00000000fed40000-0x00000000fed47fff], which spans more than MSFT0101:00 [mem 0xfed40000-0xfed44fff]
[ 7600.160865] caller RouterDebug+0x142/0x190 [corefreqk] mapping multiple BARs
[ 7600.160908] CoreFreq: ---------------- MMIO START[ 6] -------------
[ 7600.160909] CoreFreq: Offset 00000000a46049ea[0xffffffff]
[ 7600.160910] CoreFreq: ---------------- MMIO  STOP ----------------
[ 7600.160913] CoreFreq: ---------------- BAR STOP[       0] -------
[ 7600.160916] CoreFreq: ---------------- BAR START ----------------
[ 7600.160917] CoreFreq: BDF[0:0:0] + 0x48 MCHBAR[0x00000000fed10001] Enable[1]
[ 7600.160928] CoreFreq: ---------------- MMIO START[ 7] -------------
[ 7600.160929] CoreFreq: Offset 0000000014a81599[0xffffffff]
[ 7600.160930] CoreFreq: ---------------- MMIO  STOP ----------------
[ 7600.160932] CoreFreq: ---------------- BAR STOP[       0] -------
cyring commented 1 year ago

Offset 0x1400 doesn't really come up with anything.

Ok, thanks for this try.

So far, I'm out of solution. I have searched for Processor or datasheet erratum; but could not find any.

Chlorophytus commented 1 year ago

I'm working on some other projects but I tried enabling the host bridge through sysfs.

$ sudo su -c "echo 1 > /sys/devices/pci0000\:00/0000\:00\:00.0/enable"

It didn't do anything, but I'll figure this out later.

Chlorophytus commented 1 year ago

Gonna close this, I don't really know what to do from here. This isn't resolved and I'm not sure how to extract the memory controller information so I guess this is a "won't fix".