cyring
commented
4 months ago @BugReporterZ: #486 12th Gen Intel(R) Core(TM) i7-12700K
Processor [12th Gen Intel(R) Core(TM) i7-12700K]
|- Architecture [Alder Lake]
|- Vendor ID [GenuineIntel]
|- Microcode [0x00000035]
|- Signature [ 06_97]
|- Stepping [ 2]
|- Online CPU [ 20/ 20]
|- Base Clock [100.265]
|- Frequency (MHz) Ratio
Min 802.12 < 8 >
Max 3609.53 < 36 >
|- Factory [100.000]
3600 [ 36 ]
|- Performance
|- P-State
TGT 1102.91 < 11 >
|- HWP
Min 802.13 < 8 >
Max 6717.74 < 67 >
TGT AUTO < 0 >
|- Turbo Boost [ UNLOCK]
1C 5213.77 < 52 >
2C 5213.77 < 52 >
3C 5213.77 < 52 >
4C 5213.77 < 52 >
5C 5213.77 < 52 >
6C 5213.77 < 52 >
7C 5213.77 < 52 >
8C 5213.77 < 52 >
|- Hybrid [ UNLOCK]
1C 4010.63 < 40 >
2C 4010.63 < 40 >
3C 4010.63 < 40 >
4C 4010.63 < 40 >
5C 4010.63 < 40 >
6C 4010.63 < 40 >
7C 4010.63 < 40 >
8C 4010.63 < 40 >
|- Uncore [ UNLOCK]
Min 802.13 < 8 >
Max 4612.23 < 46 >
|- TDP Level [ 0:3 ]
|- Programmable [ UNLOCK]
|- Configuration [ LOCK]
|- Turbo Activation [ UNLOCK]
Nominal 3609.53 [ 36 ]
Turbo AUTO < 0 >
Instruction Set Extensions
|- 3DNow!/Ext [N/N] ADX [Y] AES [Y] AVX/AVX2 [Y/Y]
|- AMX-BF16 [N] AMX-TILE [N] AMX-INT8 [N] AMX-FP16 [N]
|- AVX512-F [N] AVX512-DQ [N] AVX512-IFMA [N] AVX512-PF [N]
|- AVX512-ER [N] AVX512-CD [N] AVX512-BW [N] AVX512-VL [N]
|- AVX512-VBMI [N] AVX512-VBMI2 [N] AVX512-VNNI [N] AVX512-ALG [N]
|- AVX512-VPOP [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N]
|- AVX512-BF16 [N] AVX-VNNI-VEX [Y] AVX-VNN-INT8 [N] AVX-NE-CONV [N]
|- AVX-IFMA [N] CMPccXADD [N] MOVDIRI [Y] MOVDIR64B [Y]
|- BMI1/BMI2 [Y/Y] CLWB [Y] CLFLUSH [Y] CLFLUSH-OPT [Y]
|- CLAC-STAC [Y] CMOV [Y] CMPXCHG8B [Y] CMPXCHG16B [Y]
|- F16C [Y] FPU [Y] FXSR [Y] LAHF-SAHF [Y]
|- ENQCMD [N] GFNI [Y] OSPKE [Y] WAITPKG [Y]
|- MMX/Ext [Y/N] MON/MWAITX [Y/N] MOVBE [Y] PCLMULQDQ [Y]
|- POPCNT [Y] RDRAND [Y] RDSEED [Y] RDTSCP [Y]
|- SEP [Y] SHA [Y] SSE [Y] SSE2 [Y]
|- SSE3 [Y] SSSE3 [Y] SSE4.1/4A [Y/N] SSE4.2 [Y]
|- SERIALIZE [Y] SYSCALL [Y] RDPID [Y] SGX [N]
|- VAES [Y] VPCLMULQDQ [Y] PREFETCH/W [Y] LZCNT [Y]
Features
|- 1 GB Pages Support 1GB-PAGES [Capable]
|- Advanced Configuration & Power Interface ACPI [Capable]
|- Advanced Programmable Interrupt Controller APIC [Capable]
|- APIC Timer Invariance ARAT [Capable]
|- Core Multi-Processing CMP Legacy [Missing]
|- L1 Data Cache Context ID CNXT-ID [Missing]
|- Direct Cache Access DCA [Missing]
|- Debugging Extension DE [Capable]
|- Debug Store & Precise Event Based Sampling DS, PEBS [Capable]
|- CPL Qualified Debug Store DS-CPL [Capable]
|- 64-Bit Debug Store DTES64 [Capable]
|- Fast Short REP CMPSB FSRC [Missing]
|- Fast Short REP MOVSB FSRM [Capable]
|- Fast Short REP STOSB FSRS [Capable]
|- Fast Zero-length REP MOVSB FZRM [Missing]
|- Fast-String Operation ERMS [Capable]
|- Fused Multiply Add FMA [Capable]
|- Flexible Return and Event Delivery FRED [Missing]
|- Hardware Feedback Interface HFI [Capable]
|- Hardware Lock Elision HLE [Missing]
|- Hyper-Threading Technology HTT [Capable]
|- History Reset HRESET [Capable]
|- Hybrid part processor HYBRID [Capable]
|- Instruction Based Sampling IBS [Missing]
|- Instruction INVPCID INVPCID [Capable]
|- Long Mode 64 bits IA64 | LM [Capable]
|- Linear Address Space Separation LASS [Missing]
|- Linear Address Masking LAM [Missing]
|- Load Kernel GS segment register LKGS [Missing]
|- LightWeight Profiling LWP [Missing]
|- Machine-Check Architecture MCA [Capable]
|- Memory Protection Extensions MPX [Missing]
|- Model Specific Registers MSR [Capable]
|- Memory Type Range Registers MTRR [Capable]
|- No-Execute Page Protection NX [Capable]
|- OS-Enabled Ext. State Management OSXSAVE [Capable]
|- Physical Address Extension PAE [Capable]
|- Page Attribute Table PAT [Capable]
|- Pending Break Enable PBE [Capable]
|- Platform Configuration PCONFIG [Capable]
|- Process Context Identifiers PCID [Capable]
|- Perfmon and Debug Capability PDCM [Capable]
|- Page Global Enable PGE [Capable]
|- Page Size Extension PSE [Capable]
|- 36-bit Page Size Extension PSE36 [Capable]
|- Processor Serial Number PSN [Missing]
|- Write Data to a Processor Trace Packet PTWRITE [Capable]
|- PREFETCHIT0/1 Instructions PREFETCHI [Missing]
|- Resource Director Technology/PQE RDT-A [Missing]
|- Resource Director Technology/PQM RDT-M [Missing]
|- Restricted Transactional Memory RTM [Missing]
|- Safer Mode Extensions SMX [Capable]
|- Self-Snoop SS [Capable]
|- Supervisor-Mode Access Prevention SMAP [Capable]
|- Supervisor-Mode Execution Prevention SMEP [Capable]
|- Thread Director TD [Capable]
|- Time Stamp Counter TSC [Invariant]
|- Time Stamp Counter Deadline TSC-DEADLINE [Capable]
|- TSX Force Abort MSR Register TSX-ABORT [Missing]
|- TSX Suspend Load Address Tracking TSX-LDTRK [Missing]
|- User-Mode Instruction Prevention UMIP [Capable]
|- Virtual Mode Extension VME [Capable]
|- Virtual Machine Extensions VMX [Capable]
|- Write Back & Do Not Invalidate Cache WBNOINVD [Missing]
|- Extended xAPIC Support x2APIC [ x2APIC]
|- Execution Disable Bit Support XD-Bit [Capable]
|- XSAVE/XSTOR States XSAVE [Capable]
|- xTPR Update Control xTPR [Capable]
Mitigation mechanisms
|- Indirect Branch Restricted Speculation IBRS [ Enable]
|- Indirect Branch Prediction Barrier IBPB [Capable]
|- Single Thread Indirect Branch Predictor STIBP [Capable]
|- Speculative Store Bypass Disable SSBD [Capable]
|- Writeback & invalidate the L1 data cache L1D-FLUSH [Capable]
|- Hypervisor - No flush L1D on VM entry L1DFL_VMENTRY_NO [ Enable]
|- Arch - Buffer Overwriting MD-CLEAR [Capable]
|- Arch - No Rogue Data Cache Load RDCL_NO [ Enable]
|- Arch - Enhanced IBRS IBRS_ALL [ Enable]
|- Arch - Return Stack Buffer Alternate RSBA [Capable]
|- Arch - No Speculative Store Bypass SSB_NO [Capable]
|- Arch - No Microarchitectural Data Sampling MDS_NO [ Enable]
|- Arch - No TSX Asynchronous Abort TAA_NO [ Enable]
|- Arch - No Page Size Change MCE PSCHANGE_MC_NO [ Enable]
|- Arch - STLB QoS STLB [ Enable]
|- Arch - Functional Safety Island FuSa [ Enable]
|- Arch - RSM in CPL0 only RSM [ Enable]
|- Arch - Split Locked Access Exception SPLA [ Enable]
|- Arch - Snoop Filter QoS Mask SNOOP_FILTER [ Enable]
|- Arch - No Fast Predictive Store Forwarding PSFD [Capable]
|- Arch - Data Operand Independent Timing Mode DOITM [Capable]
|- Arch - Not affected by SBDR or SSDP SBDR_SSDP_NO [ Enable]
|- Arch - No Fill Buffer Stale Data Propagator FBSDP_NO [ Enable]
|- Arch - No Primary Stale Data Propagator PSDP_NO [ Enable]
|- Arch - Overwrite Fill Buffer values FB_CLEAR [Capable]
|- Arch - Special Register Buffer Data Sampling SRBDS [ Unable]
|- RDRAND and RDSEED mitigation RNGDS [ Unable]
|- Restricted Transactional Memory RTM [ Unable]
|- Verify Segment for Writing instruction VERW [ Unable]
|- Arch - Restricted RSB Alternate RRSBA [ Enable]
|- Arch - No Branch Target Injection BHI_NO [Capable]
|- Arch - Legacy xAPIC Disable XAPIC_DIS [ Unable]
|- Arch - No Post-Barrier Return Stack Buffer PBRSB_NO [Capable]
|- Arch - IPRED disabled for CPL3 IPRED_DIS_U [Capable]
|- Arch - IPRED disabled for CPL0/1/2 IPRED_DIS_S [Capable]
|- Arch - RRSBA disabled for CPL3 RRSBA_DIS_U [Capable]
|- Arch - RRSBA disabled for CPL0/1/2 RRSBA_DIS_S [Capable]
|- Arch - Data Dependent Prefetcher CPL3 DDPD_U_DIS [ Unable]
|- Arch - BHI disabled for CPL0/1/2 BHI_DIS_S [ Enable]
|- No MXCSR Configuration Dependent Timing MCDT_NO [ Unable]
|- Overclocking
|- Overclocking Utilized UTILIZED [ Enable]
|- Undervolt Protection UVP [ Enable]
|- Overclocking Secure Status UNLOCKED [Capable]
Security Features
|- CPUID Key Locker KL [Capable]
|- AES Key Locker instructions AESKLE [Missing]
|- CET Shadow Stack features CET-SS [Capable]
|- CET Indirect Branch Tracking CET-IBT [Capable]
|- CET Supervisor Shadow Stack CET-SSS [Capable]
|- AES Wide Key Locker instructions WIDE_KL [Capable]
|- Software Guard SGX1 Extensions SGX1 [Missing]
|- Software Guard SGX2 Extensions SGX2 [Missing]
Technologies
|- Data Cache Unit
|- L1 Prefetcher L1 HW < ON>
|- L1 IP Prefetcher L1 HW IP < ON>
|- L1 Next Page Prefetcher L1 NPP <OFF>
|- L1 Scrubbing L1 Scrubbing <OFF>
|- Cache Prefetchers
|- L2 Prefetcher L2 HW < ON>
|- L2 Adjacent Cache Line Prefetcher L2 HW CL < ON>
|- L2 Adaptive Multipath Probability L2 AMP <OFF>
|- L2 Next Line Prefetcher L2 NLP <OFF>
|- LLC Streamer LLC < ON>
|- System Management Mode SMM-Dual [ ON]
|- Hyper-Threading HTT [ ON]
|- SpeedStep EIST < ON>
|- Dynamic Acceleration IDA [ ON]
|- Turbo Boost Max 3.0 TURBO < ON>
|- Energy Efficiency Optimization EEO <OFF>
|- Race To Halt Optimization R2H <OFF>
|- Watchdog Timer TCO <OFF>
|- Virtualization VMX [ ON]
|- I/O MMU VT-d [ ON]
|- Version [ 4.0]
|- Hypervisor [OFF]
|- Vendor ID [ N/A]
Performance Monitoring
|- Version PM [ 5]
|- Counters: General Fixed
| { 6, 0, 0 } x 48 bits 3 x 48 bits
|- Enhanced Halt State C1E < ON>
|- C1 Auto Demotion C1A < ON>
|- C3 Auto Demotion C3A <OFF>
|- C1 UnDemotion C1U < ON>
|- C3 UnDemotion C3U <OFF>
|- C6 Core Demotion CC6 <OFF>
|- C6 Module Demotion MC6 <OFF>
|- Legacy Frequency ID control FID [OFF]
|- Legacy Voltage ID control VID [OFF]
|- P-State Hardware Coordination Feedback MPERF/APERF [ ON]
|- Hardware Duty Cycling HDC [OFF]
|- Package C-States
|- Configuration Control CONFIG [ LOCK]
|- Lowest C-State LIMIT < C0>
|- I/O MWAIT Redirection IOMWAIT <Disable>
|- Max C-State Inclusion RANGE < C8>
|- Core C-States
|- C-States Base Address BAR [ 0x1814]
|- ACPI Processor C-States _CST [ 3]
|- MONITOR/MWAIT
|- State index: #0 #1 #2 #3 #4 #5 #6 #7
|- Sub C-State: 0 2 0 2 0 1 0 1
|- Monitor-Mwait Extensions EMX [Capable]
|- Interrupt Break-Event IBE [Capable]
|- Core Cycles [Capable]
|- Instructions Retired [Capable]
|- Reference Cycles [Capable]
|- Last Level Cache References [Capable]
|- Last Level Cache Misses [Capable]
|- Branch Instructions Retired [Capable]
|- Branch Mispredicts Retired [Capable]
|- Top-down slots Counter [Capable]
|- Processor Performance Control _PCT [ Enable]
|- Performance Supported States _PSS [ 0]
|- Performance Present Capabilities _PPC [ 0]
Power, Current & Thermal
|- Temperature Offset:Junction TjMax < 0: 82 C>
|- Clock Modulation ODCM <Disable>
|- DutyCycle [ 0.00%]
|- Power Management PWR MGMT [ UNLOCK]
|- Energy Policy Bias Hint < 6>
|- Energy Policy HWP EPP < 128>
|- Digital Thermal Sensor DTS [Capable]
|- Power Limit Notification PLN [Capable]
|- Package Thermal Management PTM [Capable]
|- Thermal Monitor 1 TM1 [ Enable]
|- Thermal Monitor 2 TM2 [Capable]
|- Thermal Design Power TDP [ 125 W]
|- Minimum Power Min [Missing]
|- Maximum Power Max [Missing]
|- Thermal Design Power Package < Enable>
|- Power Limit PL1 < 125 W>
|- Time Window TW1 < 2m08s>
|- Power Limit PL2 < 190 W>
|- Time Window TW2 < 2 ms>
|- Thermal Design Power Core <Disable>
|- Power Limit PL1 < 0 W>
|- Time Window TW1 < 976 us>
|- Thermal Design Power Uncore <Disable>
|- Power Limit PL1 < 0 W>
|- Time Window TW1 < 976 us>
|- Thermal Design Power DRAM <Disable>
|- Power Limit PL1 < 0 W>
|- Time Window TW1 < 976 us>
|- Thermal Design Power Platform <Disable>
|- Power Limit PL1 < 0 W>
|- Time Window TW1 < 28 s>
|- Power Limit PL2 < 0 W>
|- Time Window TW2 < 976 us>
|- Electrical Design Current EDC [Missing]
|- Thermal Design Current TDC [Missing]
|- Core Thermal Point
|- DTS Threshold #1 Threshold [Missing]
|- DTS Threshold #2 Threshold [Missing]
|- Package Thermal Point
|- DTS Threshold #1 Threshold [Missing]
|- DTS Threshold #2 Threshold [Missing]
|- Units
|- Power watt [ 0.125000000]
|- Energy joule [ 0.000061035]
|- Window second [ 0.000976562]
CPU Pkg Apic Core/Thread Caches (w)rite-Back (i)nclusive
# ID ID Hybrid ID/ID L1-Inst Way L1-Data Way L2 Way L3 Way
000:BSP 0 P 1 0 0 32768 8 49152 12 1310720 10 26214400 10
001: 0 1 P 1 0 1 32768 8 49152 12 1310720 10 26214400 10
002: 0 8 P 1 4 0 32768 8 49152 12 1310720 10 26214400 10
003: 0 9 P 1 4 1 32768 8 49152 12 1310720 10 26214400 10
004: 0 16 P 1 8 0 32768 8 49152 12 1310720 10 26214400 10
005: 0 17 P 1 8 1 32768 8 49152 12 1310720 10 26214400 10
006: 0 24 P 1 12 0 32768 8 49152 12 1310720 10 26214400 10
007: 0 25 P 1 12 1 32768 8 49152 12 1310720 10 26214400 10
008: 0 32 P 1 16 0 32768 8 49152 12 1310720 10 26214400 10
009: 0 33 P 1 16 1 32768 8 49152 12 1310720 10 26214400 10
010: 0 40 P 1 20 0 32768 8 49152 12 1310720 10 26214400 10
011: 0 41 P 1 20 1 32768 8 49152 12 1310720 10 26214400 10
012: 0 48 P 1 24 0 32768 8 49152 12 1310720 10 26214400 10
013: 0 49 P 1 24 1 32768 8 49152 12 1310720 10 26214400 10
014: 0 56 P 1 28 0 32768 8 49152 12 1310720 10 26214400 10
015: 0 57 P 1 28 1 32768 8 49152 12 1310720 10 26214400 10
016: 0 72 E 1 36 0 65536 8 32768 8 2097152 16 26214400 10
017: 0 74 E 1 37 0 65536 8 32768 8 2097152 16 26214400 10
018: 0 76 E 1 38 0 65536 8 32768 8 2097152 16 26214400 10
019: 0 78 E 1 39 0 65536 8 32768 8 2097152 16 26214400 10
Intel Z690 [7A84]
Controller #0 Dual Channel
Bus Rate 3600 MHz Bus Speed 3609 MHz DDR4 Speed 7218 MT/s
Cha CL RCDr RCDw RP RAS RRDs RRDl FAW WR RTPr WTPr CWL CKE CMD
#0 18 22 22 22 42 4 9 40 24 12 46 18 7 2T
#1 5 8 8 8 28 4 4 16 14 6 24 6 4 1T
sgRR dgRR drRR ddRR sgRW dgRW drRW ddRW sgWR dgWR drWR ddWR
#0 7 4 12 12 14 15 15 16 36 29 7 7
#1 4 4 4 4 4 4 4 4 4 4 4 4
sgWW dgWW drWW ddWW REFI RFC XS XP CPDED GEAR ECC
#0 7 4 12 12 14055 630 648 11 4 1 0
#1 4 4 4 4 4100 180 0 4 1 1 0
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0 16 2 65536 1024 16384 CMK32GX4M2D3600C18
#1 16 2 65536 1024 16384 CMK32GX4M2D3600C18
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1
Controller #1 Dual Channel
Bus Rate 3600 MHz Bus Speed 3609 MHz DDR4 Speed 7218 MT/s
Cha CL RCDr RCDw RP RAS RRDs RRDl FAW WR RTPr WTPr CWL CKE CMD
#0 18 22 22 22 42 4 9 40 24 12 46 18 7 2T
#1 5 8 8 8 28 4 4 16 14 6 24 6 4 1T
sgRR dgRR drRR ddRR sgRW dgRW drRW ddRW sgWR dgWR drWR ddWR
#0 7 4 12 12 14 15 15 16 36 29 7 7
#1 4 4 4 4 4 4 4 4 4 4 4 4
sgWW dgWW drWW ddWW REFI RFC XS XP CPDED GEAR ECC
#0 7 4 12 12 14055 630 648 11 4 1 0
#1 4 4 4 4 4100 180 0 4 1 1 0
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0 16 2 65536 1024 16384 CMK32GX4M2D3600C18
#1 16 2 65536 1024 16384 CMK32GX4M2D3600C18
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1
Linux:
|- Release [6.8.9-1-default]
|- Version [#1 SMP PREEMPT_DYNAMIC Fri May 10 08:51:14 UTC 2024 (d3445e0)]
|- Machine [x86_64]
Memory:
|- Total RAM 65530632 KB
|- Shared RAM 1313640 KB
|- Free RAM 49791360 KB
|- Buffer RAM 2712 KB
|- Total High 0 KB
|- Free High 0 KB
Clock Source < tsc>
CPU-Freq driver [ intel_pstate]
Governor [ Missing]
CPU-Idle driver [ intel_idle]
|- Idle Limit [ C10]
|- State POLL C1E C6 C8 C10
|- CPUIDLE MWAIT 0 MWAIT 0 MWAIT 0 MWAIT 0
|- Power -1 0 0 0 0
|- Latency 0 2 220 280 680
|- Residency 0 4 600 800 2000
[ 0] American Megatrends International, LLC.
[ 1] 1.H0
[ 2] 03/29/2024
[ 3] Micro-Star International Co., Ltd.
[ 4] MS-7D25
[ 5] 1.0
[ 6] D---u---s---n-
[ 7] Default string
[ 8] Default string
[ 9] Micro-Star International Co., Ltd.
[10] PRO Z690-A WIFI DDR4(MS-7D25)
[11] 1.0
[12] 0---5---L---0---8-
[13] Number Of Devices:4\Maximum Capacity:134217728 kilobytes
[14] Controller0-DIMMA1\BANK 0
[15] Controller0-DIMMA2\BANK 0
[16] Controller1-DIMMB1\BANK 0
[17] Controller1-DIMMB2\BANK 0
[18] Corsair
[19] Corsair
[20] Corsair
[21] Corsair
[22] CMK32GX4M2D3600C18
[23] CMK32GX4M2D3600C18
[24] CMK32GX4M2D3600C18
[25] CMK32GX4M2D3600C18 
BugReporterZ
paulzzh
Decoder has reporting issues among DDR4 and DDR5, two or four DIMMs, 32 or 64 bits per channel
Based on latest version
1.97.2; Owners of Intel Processors of 12th, 13th, 14th and above, please post the output of: