AMD Ryzen 9950x freq incorrect

[madoverlord40]

When single thread boosting occurs on 9950x, it goes all the way to 61 and seems to be off the chart while reporting 5676 in the upper left corner. I assume you have not yet added support for this cpu as it just released. I will keep using CoreFreq anyway hoping you will release an update soon to correct this.

Thanks.

[madoverlord40]

At this point i think its a kernel level issue. The kernel is probably not reporting the CPU correctly.

The estimation is computed from a one second interval between two TSC collects. CoreFreq relies on kernel just for the delay; the TSC being collected directly onto CPU register.

A kernel issue would be its own clock source but you would have noticed it if one second is not accurate.

Can you however try the following build option and tell if it makes a difference ?

make -j clean
make -j DELAY_TSC=0

Also, just in case of a kernel issue, can you post the output of /proc/cpuinfo (first CPU will be enough)

Ok so i just rebuilt your software using make -j DELAY_TSC=0 what info are you needing with that change?

[cyring]

doesnt it need to go through the OS to do that?

Nope, all hardware primitives are made by my own.

Ok so i just rebuilt your software using make -j DELAY_TSC=0 what info are you needing with that change?

Just want to know about BCLK. If it's still 70 or what we want 100 MHz

---

But how can it process so differently from the previous architectures, especially 7950X

BCLK 70 MHz is my main issue. TSC looks OK and counts invariantly at processor base frequency but my estimation function takes a ratio as an input parameter; ratio is broken.

[cyring]

@madoverlord40 : With the MSR-Tools installed, can you dump that series of P-State registers ?

## MSR_AMD_PSTATE_DEF_BASE
## P0
rdmsr -p 0 0xc0010064
## P1
rdmsr -p 0 0xc0010065
## P2
rdmsr -p 0 0xc0010066
## P3
rdmsr -p 0 0xc0010067
## P4
rdmsr -p 0 0xc0010068
## P5
rdmsr -p 0 0xc0010069
## P6
rdmsr -p 0 0xc001006a
## P7
rdmsr -p 0 0xc001006b

## MSR_AMD_PSTATE_CURRENT_LIMIT
rdmsr -p 0 0xc0010061

## MSR_AMD_PERF_CTL
rdmsr -p 0 0xc0010062

## MSR_AMD_PERF_STATUS
rdmsr -p 0 0xc0010063

## MSR_AMD_F17H_HW_PSTATE_STATUS
rdmsr -p 0 0xc0010293

[cyring]

Ok so using your turbo feature on core 5, ryzen master shows it to be a fast core with a white dot?

Remark: CoreFreq counts CPU number on a zero base whilst RM is one based

[madoverlord40]

Ok so using your turbo feature on core 5, ryzen master shows it to be a fast core with a white dot?

Remark: CoreFreq counts CPU number on a zero base whilst RM is one based

Oh crap lol does that invalidate the PBO max test i did for you?

[madoverlord40]

doesnt it need to go through the OS to do that?

Nope, all hardware primitives are made by my own.

Ok so i just rebuilt your software using make -j DELAY_TSC=0 what info are you needing with that change?

Just want to know about BCLK. If it's still 70 or what we want 100 MHz

But how can it process so differently from the previous architectures, especially 7950X

BCLK 70 MHz is my main issue. TSC looks OK and counts invariantly at processor base frequency but my estimation function takes a ratio as an input parameter; ratio is broken.

ITs still 70 and still showing a boost off the chart past 61. Also, my system still locks up if i leave your software running ilde for more than like 30min.

[cyring]

Ok so using your turbo feature on core 5, ryzen master shows it to be a fast core with a white dot?

Remark: CoreFreq counts CPU number on a zero base whilst RM is one based

Oh crap lol does that invalidate the PBO max test i did for you?

Luckily those adjacent cores are providing the same PBO score

[cyring]

ITs still 70 and still showing a boost off the chart past 61.

Thanks for your answer. I will debug the Coefficient Of Frequency as soon as I received the MSR dump I claimed previously.

Also, my system still locks up if i leave your software running ilde for more than like 30min.

To make sure of Linux distribution driver conflicts and kernel setup, I can suggest you boot my archlinux-corefreq.iso to download from version 1.98.2

ISO can be flashed on an USB key with a plain dd command. See instructions in wiki/Live-CD

Boot the key and when facing the startup menu, choose [Bare Metal]

And let it go...

Once CoreFreq is launched, press k for the kernel window

1. Case no driver registered at all
2. You can register all drivers. Press s for the Settings window and proceed to the Governor, CPU-Freq and CPU-idle registration
3. Case CoreFreq is governing Kernel

Q: In that configuration please let me know if system is locking up or not ?

[madoverlord40]

Ok so I booted to the thumb drive with arch linux and it installed the corefreq.ko but cpu-freq dirver will not activate in settings windows. It shows 'off' and when I try to turn it on it says error file exists. It did not lock up however I wonder if not having freq driver on is causing that?

[cyring]

when I try to turn it on it says error file exists

This means a Linux default driver is already acting as CPU-Freq.

That's why there is that [Bare Metal] entry you have to select immediately when thumb drive boots. You have a few seconds to make the selection.

Fyi, that boot menu entry attempts to blacklist all default CPU-Freq and CPU-Idle kernel modules to leave the seat to CoreFreq

~~Next, press k for Kernel window: you should read Missing for the name of drivers. If true then you are allowed to register from the Settings window.~~

To verify things are OK, reopen the Kernel window: drivers are now assigned to corefreq

In short, select [Bare Metal] during the thumb drive startup.

It did not lock up however I wonder if not having freq driver on is causing that?

That's the point of the above procedure: to find which Linux kernel module(s) CoreFreq conflicts with. Most of the time, it has been the k10temp module.

---

Q: while running the ISO, had you read a BCLK of 100 or 70 MHz ? EDIT: 70 in your screenshot.

[cyring]

As soon as you can please provide me the MSR dump as it should give me some clues to debug the frequency ratios.

[madoverlord40]

@madoverlord40 : With the MSR-Tools installed, can you dump that series of P-State registers ?

## MSR_AMD_PSTATE_DEF_BASE
## P0
rdmsr -p 0 0xc0010064
## P1
rdmsr -p 0 0xc0010065
## P2
rdmsr -p 0 0xc0010066
## P3
rdmsr -p 0 0xc0010067
## P4
rdmsr -p 0 0xc0010068
## P5
rdmsr -p 0 0xc0010069
## P6
rdmsr -p 0 0xc001006a
## P7
rdmsr -p 0 0xc001006b

## MSR_AMD_PSTATE_CURRENT_LIMIT
rdmsr -p 0 0xc0010061

## MSR_AMD_PERF_CTL
rdmsr -p 0 0xc0010062

## MSR_AMD_PERF_STATUS
rdmsr -p 0 0xc0010063

## MSR_AMD_F17H_HW_PSTATE_STATUS
rdmsr -p 0 0xc0010293

800000004ab2435c 80000000479e4258 0 0 0 0 0 0 10 0 0 4000320479

Something seems off here, do you need my CPU to be more than idle? Like do you want it at full load or is what i gave you ok?

[cyring]

@madoverlord40 Hello

Manually I'm computing the same as CoreFreq

Let's take the main P0 P-state register dump with value 800000004ab2435c

Frequency ID

FID = 0x5c = 92

Divisor ID

DID = 0x3 = 3

Coefficient Of Frequency

COF = ( FID << 1 ) / DID

COF = ( 92 * 2 ) / 3 = 61

• 9950X is specified with a base frequency of 4.3 GHz
• Confirmed by the TSC measured in Hertz at the same frequency

Base Clock

BCLK = 4300 / 61 = 70 MHz

---

This never happened with previous Zen and EPYC generations!

[madoverlord40]

I dont think thats correct though, i am not saying your math is wrong, just that 61. Both RM and bios show BLCK at 100. The highest multiplier should be 57.5 and BLCK of 100 for 5750mhz. Im also quite sure that a BLCK of 4300 would be a multiplier of 43 x 100, i dont think 61 for a multiplier is correct at all. So what i wonder is, if by chance, talking directly to the cpu when its idle, is getting you those values, maybe during idle(lower power state) it drops the blck to 70, but i think the biggest issue is a bios problem. Ive been reading online that 9000s were rushed by AMD new microcode patches are on the way to adjust performance. Could it be that bios is configuring the CPU at boot with the values you are pulling, and the problem is incorrect bios config. With that thought, ryzen master might be assuming a blck of 100 when it performs its calculations to show me the clocks of all cores when in fact its really doing what your math says. Which would explain why the 9000s seems to not quite perform as AMD said it would. So answer me this, what do you think of bios microcode being an issue with a rushed CPU release? If so that would make your calculations accurate, and bios updates might fix it in the near future.

[cyring]

So answer me this, what do you think of bios microcode being an issue with a rushed CPU release?

Honestly, you're right and I've been thinking about it ever since math blew up into my eyes. But RM, CPU-Z and HWINFO agree on the same technical answer so I can only question my calculations.

It would be interesting to try other Zen5 and other architectures like Strix Point and the next EPYC; not sure if its CPUID is confirmed and can be programmed into CoreFreq https://x.com/9550pro/status/1825870149498597760

[madoverlord40]

Yeah i wouldn't beat yourself up over it, ill watch for bios updates, and on the next bios update ill post some new screenshots of your software's behavior. In the mean time, your software basically just does not support 9000s until newer microcode comes out and maybe makes your life easier lol.

[cyring]

Yeah i wouldn't beat yourself up over it, ill watch for bios updates, and on the next bios update ill post some new screenshots of your software's behavior. In the mean time, your software basically just does not support 9000s until newer microcode comes out and maybe makes your life easier lol.

Thank you for your help.

Meanwhile another Ryzen 7 9700X got a max frequency of 6347 MHz leaked from Geekbench whereas its max Boost Clock is advertised to 5.5 GHz

Only a change in the AMD formula could explain it. But to confirm it or not, the Zen5 PPR datasheet is urgently expected. Especially if no firmware fix happens in the future.

[cyring]

@madoverlord40 Hello,

If I extend the FID to the full first 14 bits (from 0 to 13 position included)

800000004ab2435c P0 = 0x35c P0 = 860
80000000479e4258 P1 = 0x258 P1 = 600

Then I divide value by 20, I'm getting the following COF

COF(P0) = 860/20 = 43
COF(P1) = 600/20 = 30

Thus multiply by a factory BCLK of 100 MHz, frequency is as below

Freq@P0 = 43 * 100 = 4300 MHz
Freq@P1 = 30 * 100 = 3000 MHz

:-)

[cyring]

• Formula for family 1Ah would be as below

COF = (FID >> 1) / 10

where: FID is PStateDef[13:0] or PStateDef[10:0]

[cyring]

@madoverlord40 Can you pull and try latest commit of branch develop ?

I will need this output: corefreq-cli -s -n -z -n -M and two screenshots of the UI in Absolute frequency (idle and full stressed cases): corefreq-cli -Oa -t frequency

Thank you

[madoverlord40]

@madoverlord40 Can you pull and try latest commit of branch develop ?

I will need this output: corefreq-cli -s -n -z -n -M and two screenshots of the UI in Absolute frequency (idle and full stressed cases): corefreq-cli -Oa -t frequency

Thank you

Sure thing. As a software developer myself(game developer/UE5/C++) i enjoy working with other developers on projects like this. Ill go pull latest and compile, will let you know.

[madoverlord40]

Processor                                  [AMD Ryzen 9 9950X 16-Core Processor]
|- Architecture                                             [Zen5/Granite Ridge]
|- Vendor ID                                                      [AuthenticAMD]
|- Microcode                                                        [0x0b40401a]
|- Signature                                                           [  BF_44]
|- Stepping                                                            [      0]
|- Online CPU                                                          [ 32/ 32]
|- Base Clock                                                          [ 99.983]
|- Frequency            (MHz)                      Ratio                        
                 Min   2999.50                    <  30 >                       
                 Max   4299.28                    <  43 >                       
|- Factory                                                             [100.000]
                       4300                       [  43 ]                       
|- Performance                                                                  
                 TGT   4299.28                    <  43 >                       
   |- CPPC                                                                      
                 Min   3699.38                    <  37 >                       
                 Max    399.93                    <   4 >                       
                 TGT      AUTO                    <   0 >                       
   |- Boost                                                            [ UNLOCK]
                 XFR   5699.05                    [  57 ]                       
                 CPB   5699.05                    [  57 ]                       
   |- P-State                                                                   
                 P1    2999.50                    <  30 >                       
|- Uncore                                                              [   LOCK]
                 CLK   1499.75                    [  15 ]                       
                 MEM   2999.50                    [  30 ]                       

Instruction Set Extensions                                                      
|- 3DNow!/Ext [N/N]          ADX [Y]          AES [Y]  AVX/AVX2 [Y/Y] 
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|- SERIALIZE    [N]      SYSCALL [Y]        RDPID [Y]        UMIP [Y] 
|- VAES         [Y]   VPCLMULQDQ [Y]   PREFETCH/W [Y]       LZCNT [Y] 

Features                                                                        
|- 1 GB Pages Support                                      1GB-PAGES   [Capable]
|- 100 MHz multiplier Control                            100MHzSteps   [Missing]
|- Advanced Configuration & Power Interface                     ACPI   [Capable]
|- Advanced Programmable Interrupt Controller                   APIC   [Capable]
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|- Fused Multiply Add                                           FMA4   [Missing]
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|- Safer Mode Extensions                                         SMX   [Missing]
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|- Supervisor-Mode Execution Prevention                         SMEP   [Capable]
|- Trailing Bit Manipulation                                     TBM   [Missing]
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|- Time Stamp Counter Deadline                          TSC-DEADLINE   [Missing]
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|- TSX Suspend Load Address Tracking                       TSX-LDTRK   [Missing]
|- User-Mode Instruction Prevention                             UMIP   [Capable]
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|- Extended xAPIC Support                                     x2APIC   [  xAPIC]
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|- XSAVE/XSTOR States                                          XSAVE   [Capable]
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|- Extended Operation Support                                    XOP   [Missing]
Mitigation mechanisms                                                           
|- Indirect Branch Restricted Speculation                       IBRS   [Capable]
   |- IBRS Always-On preferred by processor                            [ Unable]
   |- IBRS preferred over software solution                            [Capable]
   |- IBRS provides same speculation limits                            [Capable]
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|- Single Thread Indirect Branch Predictor                     STIBP   [ Enable]
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   |- SSBD use VIRT_SPEC_CTRL register                                 [ Unable]
   |- SSBD not needed on this processor                                [ Unable]
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|- Arch - Enhanced Predictive Store Forwarding                  EPSF   [Capable]
|- Arch - Cross Processor Information Leak                XPROC_LEAK   [ Unable]
Security Features                                                               
|- CET Shadow Stack features                                  CET-SS   [Capable]
|- Secure Init and Jump with Attestation                      SKINIT   [Capable]
|- Secure Encrypted Virtualization                               SEV   [Missing]
|- SEV - Encrypted State                                      SEV-ES   [Missing]
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|- DRAM Data Scrambling                                    Scrambler   [ Enable]

Technologies                                                                    
|- Instruction Cache Unit                                                       
   |- L1 IP Prefetcher                                          L1 HW IP   < ON>
|- Data Cache Unit                                                              
   |- L1 Prefetcher                                                L1 HW   < ON>
|- Cache Prefetchers                                                            
   |- L2 Prefetcher                                                L2 HW   < ON>
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   |- L2 Stream HW Prefetcher                                  L2 Stream   < ON>
   |- L2 Up/Down Prefetcher                                   L2 Up/Down   < ON>
|- System Management Mode                                       SMM-Lock   [ ON]
|- Simultaneous Multithreading                                       SMT   [ ON]
|- PowerNow!                                                         CnQ   [ ON]
|- Core C-States                                                     CCx   [ ON]
|- Core Performance Boost                                            CPB   < ON>
|- Watchdog Timer                                                    WDT   < ON>
|- Virtualization                                                    SVM   [ ON]
   |- I/O MMU                                                      AMD-V   [ ON]
   |- Version                                                     [         0.1]
   |- Hypervisor                                                           [OFF]
   |- Vendor ID                                                   [         N/A]

Performance Monitoring                                                          
|- Version                                                        PM       [  2]
|- Counters:          General                   Fixed                           
|           {  6,  4, 16 } x 48 bits            3 x 64 bits                     
|- Enhanced Halt State                                           C1E       <OFF>
|- C2 UnDemotion                                                 C2U       < ON>
|- C3 UnDemotion                                                 C3U       < ON>
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|- Package C6 State                                              PC6       < ON>
|- Legacy Frequency ID control                                   FID       [OFF]
|- Legacy Voltage ID control                                     VID       [OFF]
|- P-State Hardware Coordination Feedback                MPERF/APERF       [ ON]
|- Core C-States                                                                
   |- C-States Base Address                                      BAR   [ 0x413 ]
|- ACPI Processor C-States                                      _CST   [      3]
|- MONITOR/MWAIT                                                                
   |- State index:    #0    #1    #2    #3    #4    #5    #6    #7              
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Power, Current & Thermal                                                        
|- Temperature Offset:Junction                                 TjMax [ 49: 95 C]
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|- Digital Thermal Sensor                                        DTS   [Capable]
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|- Thermal Monitor 2                                             HTC   [ Enable]
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|- Package Power Tracking                                        PPT   [Missing]
|- Electrical Design Current                                     EDC   [Missing]
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|- Core Thermal Point                                                           
|- Package Thermal Point                                                        
   |- Thermal Monitor Trip                                     Limit   [  115 C]
   |- HTC Temperature Limit                                    Limit   [  127 C]
   |- HTC Temperature Hysteresis                           Threshold   [    2 C]
|- Units                                                                        
   |- Power                                               watt   [      Missing]
   |- Energy                                             joule   [  0.000015259]
   |- Window                                            second   [  0.000976562]

|- Collaborative Processor Performance Control                  CPPC       < ON>
   |- Capabilities     Lowest      Efficient     Guaranteed        Highest      
   |- CPU #0     399.93 (  4)  1899.68 ( 19)  2799.53 ( 28)  5199.13 ( 52)      
   |- CPU #1     399.94 (  4)  1899.70 ( 19)  2799.56 ( 28)  5299.17 ( 53)      
   |- CPU #2     399.94 (  4)  1899.70 ( 19)  2799.56 ( 28)  4899.24 ( 49)      
   |- CPU #3     399.93 (  4)  1899.68 ( 19)  2799.54 ( 28)  4799.20 ( 48)      
   |- CPU #4     399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  5299.12 ( 53)      
   |- CPU #5     399.94 (  4)  1899.70 ( 19)  2799.56 ( 28)  5099.20 ( 51)      
   |- CPU #6     399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  4599.25 ( 46)      
   |- CPU #7     399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  4699.23 ( 47)      
   |- CPU #8     399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  3999.35 ( 40)      
   |- CPU #9     399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  4499.26 ( 45)      
   |- CPU #10    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  4199.32 ( 42)      
   |- CPU #11    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  4399.28 ( 44)      
   |- CPU #12    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  3899.36 ( 39)      
   |- CPU #13    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  4299.30 ( 43)      
   |- CPU #14    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  3799.38 ( 38)      
   |- CPU #15    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  3699.40 ( 37)      
   |- CPU #16    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  5199.14 ( 52)      
   |- CPU #17    399.94 (  4)  1899.69 ( 19)  2799.55 ( 28)  5299.14 ( 53)      
   |- CPU #18    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  4899.20 ( 49)      
   |- CPU #19    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  4799.22 ( 48)      
   |- CPU #20    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  5299.13 ( 53)      
   |- CPU #21    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  5099.17 ( 51)      
   |- CPU #22    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  4599.25 ( 46)      
   |- CPU #23    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  4699.23 ( 47)      
   |- CPU #24    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  3999.35 ( 40)      
   |- CPU #25    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  4499.27 ( 45)      
   |- CPU #26    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  4199.31 ( 42)      
   |- CPU #27    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  4399.28 ( 44)      
   |- CPU #28    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  3899.36 ( 39)      
   |- CPU #29    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  4299.30 ( 43)      
   |- CPU #30    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  3799.38 ( 38)      
   |- CPU #31    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  3699.40 ( 37)      

                              Zen UMC  [14E0]                              
Controller #0                                                Dual Channel  
 Bus Rate  3000 MHz       Bus Speed 3000 MHz           DDR5 Speed 6000 MT/s

 Cha   CL  RCDr RCDw  RP  RAS   RC  RRDs RRDl FAW  WTRs WTRl  WR  clRR clWW
  #0   32   39   39   39  102  146    8   15   32    8   30   90    8   23 
  #1   32   39   39   39  102  146    8   15   32    8   30   90    8   23 
      CWL  RTP RdWr WrRd scWW sdWW ddWW scRR sdRR ddRR drRR drWW drWR drRRD
  #0   30   23   21    8    1   10   10    1   11   11    0    0    0    0 
  #1   30   23   22    8    1   10   10    1   11   11    0    0    0    0 
      REFI RFC1 RFC2 RFCsb RCPB RPPB BGS:Alt  Ban  Page  CKE  CMD  GDM  ECC
  #0 11677  312  192  390   0    0    ON OFF  R0W0   0    0   1T    ON   0 
  #1 11677  312  192  390   0    0    ON OFF  R0W0   0    0   1T    ON   0 
      MRD:PDA   MOD:PDA  WRMPR STAG PDM RDDATA WRD  WRL  RDL  XS   XP CPDED
  #0   42  32    42  32    24    7 0:F:1   20   6   18   36  914   23   15 
  #1   42  32    42  32    24    7 0:F:1   20   6   18   36  914   23   15 

 DIMM Geometry for channel #0                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0                                                                  
       #1    32    1     65536      1024          16384    F5-6400J3239G32G
 DIMM Geometry for channel #1                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0                                                                  
       #1    32    1     65536      1024          16384    F5-6400J3239G32G

[madoverlord40]

corefreq-cli -Oa -t frequency

Its usually 3600 all the way down idle, when it hit the screenshot button one core boosted lol

[madoverlord40]

[madoverlord40]

FYI i think its show 5825 because i have a +100 boost clock in bios, but it seems to want to not give the entire 100 over.

[cyring]

FYI i think its show 5825 because i have a +100 boost clock in bios, but it seems to want to not give the entire 100 over.

Thanks for your returns

It works much better. CPU and Memory frequencies are getting accurate 😊

---

On screenshots I'm noticing that Vcore is going in the opposite direction of the system load.

That's something I had fixed for 7950X in issue #496 without knowing the root cause.

But previously on 9950X we used to have a coherent voltage Core.

So what did happen in your 9950X configuration? BIOS? Microcode? Hardware change?

[madoverlord40]

the only thing i have done is lowered my curve optimizer value down for stability. This may have changed the voltages curves for you.

[cyring]

the only thing i have done is lowered my curve optimizer value down for stability. This may have changed the voltages curves for you.

If you cancel this change, are you reading back the good Vcore?

[madoverlord40]

Hmm i did notice that one of my curve optimizer settings recently had my system hard locked, and i had to clear cmos to get it to post again. At the time i was just trying to find the limits it would boot at. After cmos clear i put PBO back on and curve optimizer -20. Maybe the recent clear cmos changed something? Should i just load setup defaults and get you new screen shots with no bios settings changed?

[cyring]

FYI i think its show 5825 because i have a +100 boost clock in bios, but it seems to want to not give the entire 100 over.

You mean you have set a frequency ratio of 58 in BIOS but that value is not shown in the corefreq-cli -s output and not in the UI [Processor] window ?

---

Observe that you can increase the UI ruler with a build parameter. For example to display up to a maximum of 60

make -j UI_RULER_MAXIMUM=60

[madoverlord40]

You mean you have set a frequency ratio of 58 in BIOS but that value is not shown in the corefreq-cli -s output and not in the UI [Processor] window ?

No i mean i added 100 to boost clock override in PBO, which means its max boost clock gets bumped up by 100 when PBO fires. I didnt change any multipliers. Would it be helpful if in my bios, i reset everything to setup defaults incase my bios custom settings are throwing off your calculations?

[madoverlord40]

Here are some custom bios settings i have for PBO if it helps you:

Here i turned up the LLC to try and balance high curve optimizer:

Maybe these settings are making it harder for you to get VCore values you expect?

[madoverlord40]

Yeah i see what you mean now, this next one is your software with no parameters, showing relative, check out the V at the bottom:

[cyring]

Maybe these settings are making it harder for you to get VCore values you expect?

Yes I believe they change the relation between the VID and the computed voltage.

AMD has specified a voltage formula for Zen and that's the only one I know. This formula does not take into account any optimizer.

Please let me know if setting back the BIOS to the voltage stock options is showing the right Vcore in CoreFreq ?

[madoverlord40]

Maybe these settings are making it harder for you to get VCore values you expect?

Yes I believe they change the relation between the VID and the computed voltage.

AMD has specified a voltage formula for Zen and that's the only one I know. This formula does not take into account any optimizer.

Please let me know if setting back the BIOS to the voltage stock options is showing the right Vcore in CoreFreq ?

Ok i will go set LLC to auto, and set PBO to just enabled, Ill also remove the boost clock +100 and set the curve optimizer to off and i will get you some new screenshots.

[cyring]

Yeah i see what you mean now, this next one is your software with no parameters, showing relative, check out the V at the bottom:

Indeed, as you can see a Vcore of 1.39 is not feasible when Processor is idle. Thus my request to test with stock options.

[madoverlord40]

Yeah i see what you mean now, this next one is your software with no parameters, showing relative, check out the V at the bottom:

Indeed, as you can see a Vcore of 1.39 is not feasible when Processor is idle. Thus my request to test with stock options.

Ok all i see is that the VCore is higher now, here is LLC auto, curve optimizer off, PBO enabled not max: While screen capturing i saw VCore spike to 1.45 without frequency load to match. Also it seems to bounce back and fourth from 0.88 to 1.43ish without frequency load to match.

[madoverlord40]

This is using your software to turn on turbo for all cores, nearly normal bios, no options passed to your software:

When i stop it, the V goes down to 0.88 for a short time the spikes back up to 1.43ish and stays there with no load.

[cyring]

@madoverlord40 0.88 when idle, despite LLC, confirms a good reading. Thank you for this test.

Unfortunately I'm not aware of Registers to compensate voltage when BIOS tricks are enabled.

[cyring]

@madoverlord40 Voltage subject transfered to issue #506 as Optimizer concerns more architectures

[madoverlord40]

@madoverlord40 Voltage subject transfered to issue #506 as Optimizer concerns more architectures

Ok cool.

[huajian628]

[huajian628]

[huajian628]

"Why can't I compile version 1.98.3 correctly on the rocky9.2 system with a 9950X CPU?"

[huajian628]

"Should I switch to a lower version?"

[huajian628]

[huajian628]

1.96.5version is ok but no temperature

[cyring]

"Why can't I compile version 1.98.3 correctly on the rocky9.2 system with a 9950X CPU?"

Edit file at these lines:

https://github.com/cyring/CoreFreq/blob/85b1e626183986c3bdfcc9b2bb046e8f24a13882/x86_64/corefreqk.c#L24125

Replace the build condition with:

#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 4, 0) \
 || (defined(RHEL_MAJOR) && (RHEL_MAJOR >= 9) \
 && (RHEL_MINOR > 2) && (RHEL_MINOR < 99))

Save file and rebuild all

make -j clean
make -j

[huajian628]

i try

[huajian628]