cyring
commented
1 month ago Notes: 1. For non-binary densities, a quarter of the row address space is invalid. When the MSB address bit is HIGH, the MSB-1 address must be LOW.
Open cyring opened 1 month ago
cyring
commented
1 month ago Notes: 1. For non-binary densities, a quarter of the row address space is invalid. When the MSB address bit is HIGH, the MSB-1 address must be LOW.
nooberfsh
commented
2 days ago Hi. 9950x, 2 * 48G
# channel 0
[0x00050100] READ(smu) = 0x80000701 (2147485441)
60 56 52 48 44 40 36 32 28 24 20 16 12 08 04 00
0000 0000 0000 0000 0000 0000 0000 0000 1000 0000 0000 0000 0000 0111 0000 0001
# channel 1
[0x00150100] READ(smu) = 0x80000701 (2147485441)
60 56 52 48 44 40 36 32 28 24 20 16 12 08 04 00
0000 0000 0000 0000 0000 0000 0000 0000 1000 0000 0000 0000 0000 0111 0000 0001@nooberfsh Thanks for your dump. Unfortunately I'm finding no hint in this register.
Can you show me how your 9950X memory controller is decoded with:
corefreq-cli -k -n -B -n -M@cyring Sure
Linux:
|- Release [6.11.6-arch1-1]
|- Version [#1 SMP PREEMPT_DYNAMIC Fri, 01 Nov 2024 03:30:41 +0000]
|- Machine [x86_64]
Memory:
|- Total RAM 96393508 KB
|- Shared RAM 379760 KB
|- Free RAM 89599260 KB
|- Buffer RAM 139252 KB
|- Total High 0 KB
|- Free High 0 KB
Clock Source < tsc>
CPU-Freq driver [ amd-pstate-epp]
Governor [ Missing]
CPU-Idle driver [ acpi_idle]
|- Idle Limit [ C3]
|- State POLL C1 C2 C3
|- CPUIDLE ACPI FF ACPI IO ACPI IO
|- Power -1 0 0 0
|- Latency 0 1 18 350
|- Residency 0 2 36 700
[ 0] American Megatrends International, LLC.
[ 1] 1.L0
[ 2] 10/16/2024
[ 3] Micro-Star International Co., Ltd.
[ 4] MS-7D70
[ 5] 1.0
[ 6] T---e---l--- ---O---M-
[ 7] To be filled by O.E.M.
[ 8] To be filled by O.E.M.
[ 9] Micro-Star International Co., Ltd.
[10] MPG X670E CARBON WIFI (MS-7D70)
[11] 1.0
[12] 0---0---O---3---0-
[13] Number Of Devices:4\Maximum Capacity:134217728 kilobytes
[14]
[15] DIMMA2\P0 CHANNEL A
[16]
[17] DIMMB2\P0 CHANNEL B
[18]
[19] Unknown
[20]
[21] Unknown
[22]
[23]
[24]
[25]
Zen UMC [14E0]
Controller #0 Dual Channel
Bus Rate 3000 MHz Bus Speed 2994 MHz DDR5 Speed 5988 MT/s
Cha CL RCDr RCDw RP RAS RC RRDs RRDl FAW WTRs WTRl WR clRR clWW
#0 30 36 36 36 76 115 8 15 32 8 30 90 8 23
#1 30 36 36 36 76 115 8 15 32 8 30 90 8 23
CWL RTP RdWr WrRd scWW sdWW ddWW scRR sdRR ddRR drRR drWW drWR drRRD
#0 28 23 20 8 1 10 10 1 11 11 0 0 0 0
#1 28 23 21 8 1 10 10 1 11 11 0 0 0 0
REFI RFC1 RFC2 RFCsb RCPB RPPB BGS:Alt Ban Page CKE CMD GDM ECC
#0 11677 312 192 390 0 0 ON OFF R0W0 0 0 1T ON 0
#1 11677 312 192 390 0 0 ON OFF R0W0 0 0 1T ON 0
MRD:PDA MOD:PDA WRMPR STAG PDM RDDATA WRD WRL RDL XS XP CPDED
#0 42 32 42 32 24 7 0:F:0 18 6 16 36 914 23 15
#1 42 32 42 32 24 7 0:F:0 18 6 16 36 914 23 15
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 32 1 131072 1024 32768
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 32 1 131072 1024 32768 Hi. 9950x, 2 * 48G
Hello,
Can I have this long list of dump registers based on these specifications
# UMC::BaseAddr
## Channel 0
./zencli smu 0x50000
./zencli smu 0x50004
./zencli smu 0x50008
./zencli smu 0x5000c
## Channel 1
./zencli smu 0x150000
./zencli smu 0x150004
./zencli smu 0x150008
./zencli smu 0x15000c
# UMC::BaseAddrSec
## Channel 0
./zencli smu 0x50010
./zencli smu 0x50014
./zencli smu 0x50018
./zencli smu 0x5001c
## Channel 1
./zencli smu 0x150010
./zencli smu 0x150014
./zencli smu 0x150018
./zencli smu 0x15001c
# UMC::AddrMask
## Channel 0
./zencli smu 0x50020
./zencli smu 0x50024
./zencli smu 0x50028
./zencli smu 0x5002c
## Channel 1
./zencli smu 0x150020
./zencli smu 0x150024
./zencli smu 0x150028
./zencli smu 0x15002c
# UMC::AddrMaskSec
## Channel 0
./zencli smu 0x50030
./zencli smu 0x50034
./zencli smu 0x50038
./zencli smu 0x5003c
## Channel 1
./zencli smu 0x150030
./zencli smu 0x150034
./zencli smu 0x150038
./zencli smu 0x15003cAnd also
# UMC::AddrCfg
## Channel 0
./zencli smu 0x50040
./zencli smu 0x50044
./zencli smu 0x50048
./zencli smu 0x5004c
## Channel 1
./zencli smu 0x150040
./zencli smu 0x150044
./zencli smu 0x150048
./zencli smu 0x15004c
# UMC::DimmCfg
## Channel 0
./zencli smu 0x50090
./zencli smu 0x50094
## Channel 1
./zencli smu 0x150090
./zencli smu 0x150094Sure, but I can't access my PC until this weekend, I'll post the result as soon as possible.
DDR5 Query
What is “non-binary” memory?
To decode the 24GB or 48GB DIMM geometry, can anyone dump some registers ?
[AMD] Zen 4 or 5
DdrTypebits-field I expect to find some new DDR5 type values or something in theReservedpart[Intel]