Closed EUA closed 3 months ago
cyring
commented
5 years ago Hello,
C3/C6/C7 are implemented for Intel Processors only. The UI just shows the placeholder for counters as zero.
It might be feasible to read above C3 but I don't read those counters specifications in AMD Zen doc.
CC6 & PC6 are undocumented bits. See project ZenState
C2 is something I have to look at...
cyring
commented
5 years ago Based on cpuidle.c source code, can you print :
cat /sys/devices/system/cpu/cpu0/cpuidle/state?/nameBy the way, you should read the same in the 'Kernel Data' window
EUA
commented
5 years ago # cat /sys/devices/system/cpu/cpu0/cpuidle/state?/name
POLL
C1
C2I think RyZen micro-code does not export all C states to Linux Kernel.
cyring
commented
5 years ago Is this the same with Windows software ? Such as ThrottleStop
EUA
commented
5 years ago Oopps. CPU is not supported by ThrottleStop
cyring
commented
5 years ago Perhaps in the EFI/BIOS or the AMD software, but googling for Zen C-States doesn't show any monitoring of deep idle states.
cyring
commented
5 years ago I'm closing this issue but feel to try the experimental Zen overclocking @ issue #87
cyring
commented
4 years ago Hello, Among the last changes in issue #195 , an I/O ASM access to the FCH have been added: can you please check if the last CoreFreq version is starting fine ? Thank you
EUA
commented
4 months ago Hello. Don't know why but I missed this notifications.
My older board is broken. Will try solder new mosfets next week...
Now I have 8600G CPU. I compiled from git-trunk and saw that;
Still only C0 and C1 available while cpupower idle-info shows C2 and C3 states for my 8600G
Also at windows, HWiNFO able to show C6 states of processors proper.
CoreFreq able to show C2/3/6 is enabled:
Don't know if "I/O ASM access to the FCH" improvements are enabled supported on my board/cpu. Might be, they work on old architectures. If any data required to you for implement your program, I can send any kind of dump.
When I able to repair my AM4 board, try to run cpufreqd on it to see if there are any improvement on C states with x1700 and 5700G CPUs. Thanks.
cyring
commented
4 months ago @EUA
CoreFreq able to show C2/3/6 is enabled:
Here Core C6 State and Package C6 State mean they are detected as enabled (from Registers)
However I still miss the hardware counters specification since Zen 1 to read straight from some registers the number of cycles elapsed per C-States.
With Intel processors, those values are easily read from MSR registers.
See the great article from Mete Balci: A Minimum Complete Tutorial of CPU Power Management, C-states and P-states
Meanwhile I had implemented software kernel counters down to C6
( make sure to pull latest commits from branch master )
Just start driver with these parameters:
insmod build/corefreqk.ko Register_ClockSource=1 Register_Governor=1 Register_CPU_Idle=1 Register_CPU_Freq=1
echo "corefreq_tsc" > /sys/devices/system/clocksource/clocksource0/current_clocksourceYou can then alternate as will the idle limit from the UI window named Kernel
You will have to unload or prevent any other driver to act as CPU-Idle, CPU-Freq and ClockSource.
They have to be Missing prior registering CoreFreq
See Wiki/CoreFreq as the Clock Source, CPU Freq and CPU Idle driver
When done, please provide me, using Mardown format, the output of the following CLI
build/corefreq-cli -s -n -m -n -B -n -M -n -k -n -C 1 -n -i 1 -n -V 1 -n -W 1 -n -c 1Hello there. Thanks for quick reply. I just loaded my built kernel module with parameters that you provided but... Still same result. only C1 and C2 available. Why? Probably some other things like amd_pstate driver loaded already into kernel. But I can't find amd_pstate module on my modules directory. Probably it's delivered in the kernel that I use (Arch Zen kernel). Not compiled as a module on my PC. Will try with standard kernel also. Do you know which other kernel modules could interfere with it?
At settings, CPU-IDLE driver and CPU-FREQ driver shows OFF while "CPU-IDLE route" shown as I/O
It's sad thing that learning AMD (still) do not exposes it's C states via MSRs, which is super easy to work with it.
Anyway, Here is the output of my CPU/System;
build/corefreq-cli -s -n -m -n -B -n -M -n -k -n -C 1 -n -i 1 -n -V 1 -n -W 1 -n -c 1
Processor [AMD Ryzen 5 8600G w/ Radeon 760M Graphics]
|- Architecture [Zen4/Hawk Point]
|- Vendor ID [AuthenticAMD]
|- Microcode [0x0a705203]
|- Signature [ AF_75]
|- Stepping [ 2]
|- Online CPU [ 12/ 12]
|- Base Clock [101.168]
|- Frequency (MHz) Ratio
Min 1618.69 < 16 >
Max 4350.24 < 43 >
|- Factory [100.000]
4300 [ 43 ]
|- Performance
|- P-State
TGT 4350.24 < 43 >
|- CPPC
Min 3844.40 < 38 >
Max 4350.24 < 43 >
TGT AUTO < 0 >
|- Turbo Boost [ UNLOCK]
XFR 5058.42 [ 50 ]
CPB 5058.42 [ 50 ]
1C 2225.70 < 22 >
2C 1618.69 < 16 >
|- Uncore [ LOCK]
CLK 2023.37 [ 20 ]
MEM 4046.73 [ 40 ]
Instruction Set Extensions
|- 3DNow!/Ext [N/N] ADX [Y] AES [Y] AVX/AVX2 [Y/Y]
|- AVX512-F [Y] AVX512-DQ [Y] AVX512-IFMA [Y] AVX512-PF [N]
|- AVX512-ER [N] AVX512-CD [Y] AVX512-BW [Y] AVX512-VL [Y]
|- AVX512-VBMI [Y] AVX512-VBMI2 [Y] AVX512-VNNI [Y] AVX512-ALG [Y]
|- AVX512-VPOP [Y] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N]
|- AVX512-BF16 [Y] AVX-VNNI-VEX [N] AVX-FP128 [N] AVX-FP256 [Y]
|- BMI1/BMI2 [Y/Y] CLWB [Y] CLFLUSH [Y] CLFLUSH-OPT [Y]
|- CLAC-STAC [Y] CMOV [Y] CMPXCHG8B [Y] CMPXCHG16B [Y]
|- F16C [Y] FPU [Y] FXSR [Y] LAHF-SAHF [Y]
|- MMX/Ext [Y/Y] MON/MWAITX [Y/Y] MOVBE [Y] PCLMULQDQ [Y]
|- POPCNT [Y] RDRAND [Y] RDSEED [Y] RDTSCP [Y]
|- SEP [Y] SHA [Y] SSE [Y] SSE2 [Y]
|- SSE3 [Y] SSSE3 [Y] SSE4.1/4A [Y/Y] SSE4.2 [Y]
|- SERIALIZE [N] SYSCALL [Y] RDPID [Y] UMIP [Y]
|- VAES [Y] VPCLMULQDQ [Y] PREFETCH/W [Y] LZCNT [Y]
Features
|- 1 GB Pages Support 1GB-PAGES [Capable]
|- 100 MHz multiplier Control 100MHzSteps [Missing]
|- Advanced Configuration & Power Interface ACPI [Capable]
|- Advanced Programmable Interrupt Controller APIC [Capable]
|- Advanced Virtual Interrupt Controller AVIC [Capable]
|- APIC Timer Invariance ARAT [Capable]
|- LOCK prefix to read CR8 AltMov [Capable]
|- Clear Zero Instruction CLZERO [Capable]
|- Core Multi-Processing CMP Legacy [Capable]
|- L1 Data Cache Context ID CNXT-ID [Missing]
|- Collaborative Processor Performance Control CPPC [Capable]
|- Direct Cache Access DCA [Missing]
|- Debugging Extension DE [Capable]
|- Debug Store & Precise Event Based Sampling DS, PEBS [Missing]
|- CPL Qualified Debug Store DS-CPL [Missing]
|- 64-Bit Debug Store DTES64 [Missing]
|- Fast Short REP MOVSB FSRM [Capable]
|- Fast-String Operation ERMS [Capable]
|- Fused Multiply Add FMA4 [Missing]
|- Fused Multiply Add FMA [Capable]
|- Hardware Lock Elision HLE [Missing]
|- Hyper-Threading Technology HTT [Capable]
|- Hardware P-state control HwP [Capable]
|- Instruction Based Sampling IBS [Capable]
|- Instruction INVLPGB INVLPGB [Missing]
|- Instruction INVPCID INVPCID [Capable]
|- Long Mode 64 bits IA64 | LM [Capable]
|- LightWeight Profiling LWP [Missing]
|- Memory Bandwidth Enforcement MBE [Capable]
|- Machine-Check Architecture MCA [Capable]
|- Instruction MCOMMIT MCOMMIT [Missing]
|- Model Specific Registers MSR [Capable]
|- Memory Type Range Registers MTRR [Capable]
|- No-Execute Page Protection NX [Capable]
|- OS-Enabled Ext. State Management OSXSAVE [Capable]
|- OS Visible Work-around OSVW [Capable]
|- Physical Address Extension PAE [Capable]
|- Page Attribute Table PAT [Capable]
|- Pending Break Enable PBE [Missing]
|- Process Context Identifiers PCID [Missing]
|- Perfmon and Debug Capability PDCM [Missing]
|- Page Global Enable PGE [Capable]
|- Page Size Extension PSE [Capable]
|- 36-bit Page Size Extension PSE36 [Capable]
|- Processor Serial Number PSN [Missing]
|- Resource Director Technology/PQE RDT-A [Capable]
|- Resource Director Technology/PQM RDT-M [Capable]
|- Read Processor Register at User level RDPRU [Capable]
|- Restricted Transactional Memory RTM [Missing]
|- Safer Mode Extensions SMX [Missing]
|- Self-Snoop SS [Missing]
|- Supervisor-Mode Access Prevention SMAP [Capable]
|- Supervisor-Mode Execution Prevention SMEP [Capable]
|- Trailing Bit Manipulation TBM [Missing]
|- Translation Cache Extension TCE [Capable]
|- Time Stamp Counter TSC [Invariant]
|- Time Stamp Counter Deadline TSC-DEADLINE [Missing]
|- TSX Force Abort MSR Register TSX-ABORT [Missing]
|- TSX Suspend Load Address Tracking TSX-LDTRK [Missing]
|- User-Mode Instruction Prevention UMIP [Capable]
|- Virtual Mode Extension VME [Capable]
|- Virtual Machine Extensions VMX [Missing]
|- Write Back & Do Not Invalidate Cache WBNOINVD [Capable]
|- Extended xAPIC Support x2APIC [ xAPIC]
|- AVIC controller for x2APIC x2AVIC [Capable]
|- XSAVE/XSTOR States XSAVE [Capable]
|- xTPR Update Control xTPR [Missing]
|- Extended Operation Support XOP [Missing]
Mitigation mechanisms
|- Indirect Branch Restricted Speculation IBRS [Capable]
|- IBRS Always-On preferred by processor [ Unable]
|- IBRS preferred over software solution [Capable]
|- IBRS provides same speculation limits [Capable]
|- Indirect Branch Prediction Barrier IBPB [Capable]
|- Single Thread Indirect Branch Predictor STIBP [ Enable]
|- Speculative Store Bypass Disable SSBD [Capable]
|- SSBD use VIRT_SPEC_CTRL register [ Unable]
|- SSBD not needed on this processor [ Unable]
|- No Branch Type Confusion BTC_NO [ Unable]
|- BTC on Non-Branch instruction BTC-NOBR [Capable]
|- Limited Early Redirect Window AGENPICK [ Unable]
|- Arch - No Fast Predictive Store Forwarding PSFD [Capable]
|- Arch - Enhanced Predictive Store Forwarding EPSF [Capable]
|- Arch - Cross Processor Information Leak XPROC_LEAK [ Unable]
Security Features
|- CET Shadow Stack features CET-SS [Capable]
|- Secure Init and Jump with Attestation SKINIT [Capable]
|- Secure Encrypted Virtualization SEV [Missing]
|- SEV - Encrypted State SEV-ES [Missing]
|- SEV - Secure Nested Paging SEV-SNP [Missing]
|- Guest Mode Execute Trap GMET [Capable]
|- Supervisor Shadow Stack SSS [Capable]
|- VM Permission Levels VMPL [Missing]
|- VMPL Supervisor Shadow Stack VMPL-SSS [Missing]
|- Secure Memory Encryption SME [Capable]
|- Transparent SME TSME [ Enable]
|- Secure Multi-Key Memory Encryption SME-MK [Missing]
|- DRAM Data Scrambling Scrambler [ Enable]
Technologies
|- Instruction Cache Unit
|- L1 IP Prefetcher L1 HW IP < ON>
|- Data Cache Unit
|- L1 Prefetcher L1 HW < ON>
|- Cache Prefetchers
|- L2 Prefetcher L2 HW < ON>
|- L1 Stride Prefetcher L1 Stride < ON>
|- L1 Region Prefetcher L1 Region < ON>
|- L1 Burst Prefetch Mode L1 Burst < ON>
|- L2 Stream HW Prefetcher L2 Stream < ON>
|- L2 Up/Down Prefetcher L2 Up/Down < ON>
|- System Management Mode SMM-Lock [ ON]
|- Simultaneous Multithreading SMT [ ON]
|- PowerNow! CnQ [ ON]
|- Core C-States CCx [ ON]
|- Core Performance Boost CPB < ON>
|- Watchdog Timer WDT < ON>
|- Virtualization SVM [ ON]
|- I/O MMU AMD-V [ ON]
|- Version [ 0.1]
|- Hypervisor [OFF]
|- Vendor ID [ N/A]
Performance Monitoring
|- Version PM [ 2]
|- Counters: General Fixed
| { 6, 6, 4 } x 48 bits 3 x 64 bits
|- Enhanced Halt State C1E <OFF>
|- C2 UnDemotion C2U < ON>
|- C3 UnDemotion C3U < ON>
|- Core C6 State CC6 < ON>
|- Package C6 State PC6 < ON>
|- Legacy Frequency ID control FID [OFF]
|- Legacy Voltage ID control VID [OFF]
|- P-State Hardware Coordination Feedback MPERF/APERF [ ON]
|- Core C-States
|- C-States Base Address BAR [ 0x413 ]
|- ACPI Processor C-States _CST [ 3]
|- MONITOR/MWAIT
|- State index: #0 #1 #2 #3 #4 #5 #6 #7
|- Sub C-State: 1 1 0 0 0 0 0 0
|- Monitor-Mwait Extensions EMX [Capable]
|- Interrupt Break-Event IBE [Capable]
|- Core Cycles [Capable]
|- Instructions Retired [Capable]
|- Reference Cycles [Capable]
|- Last Level Cache References [Capable]
|- Global Time Stamp Counter [Missing]
|- Data Fabric Performance Counter [Capable]
|- Core Performance Counter [Capable]
|- Processor Performance Control _PCT [ Enable]
|- Performance Supported States _PSS [ 3]
|- Performance Present Capabilities _PPC [ 0]
|- Continuous Performance Control _CPC [Missing]
Power, Current & Thermal
|- Temperature Offset:Junction TjMax [ 0: 0 C]
|- CPPC Energy Preference EPP < 0>
|- Digital Thermal Sensor DTS [Capable]
|- Power Limit Notification PLN [Missing]
|- Package Thermal Management PTM [Missing]
|- Thermal Monitor 1 TTP [ Enable]
|- Thermal Monitor 2 HTC [ Enable]
|- Thermal Design Power TDP [Missing]
|- Minimum Power Min [Missing]
|- Maximum Power Max [Missing]
|- Thermal Design Power Package [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 0 ns]
|- Power Limit PL2 [ 0 W]
|- Time Window TW2 [ 0 ns]
|- Thermal Design Power Core [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 0 ns]
|- Thermal Design Power Uncore [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 0 ns]
|- Thermal Design Power DRAM [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 0 ns]
|- Thermal Design Power Platform [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 0 ns]
|- Power Limit PL2 [ 0 W]
|- Time Window TW2 [ 0 ns]
|- Package Power Tracking PPT [Missing]
|- Electrical Design Current EDC [Missing]
|- Thermal Design Current TDC [Missing]
|- Core Thermal Point
|- Package Thermal Point
|- Thermal Monitor Trip Limit [ 115 C]
|- HTC Temperature Limit Limit [ 127 C]
|- HTC Temperature Hysteresis Threshold [ 2 C]
|- Units
|- Power watt [ 0.125000000]
|- Energy joule [ 0.000015259]
|- Window second [ 0.000976562]
CPU Pkg Apic Core/Thread Caches (w)rite-Back (i)nclusive
# ID ID CCD CCX ID/ID L1-Inst Way L1-Data Way L2 Way L3 Way
000:BSP 0 0 0 0 0 32 8 32 8 1024 8 i 16384 16w
001: 0 2 0 0 1 0 32 8 32 8 1024 8 i 16384 16w
002: 0 4 0 0 2 0 32 8 32 8 1024 8 i 16384 16w
003: 0 6 0 0 3 0 32 8 32 8 1024 8 i 16384 16w
004: 0 8 0 1 4 0 32 8 32 8 1024 8 i 16384 16w
005: 0 10 0 1 5 0 32 8 32 8 1024 8 i 16384 16w
006: 0 1 0 0 0 1 32 8 32 8 1024 8 i 16384 16w
007: 0 3 0 0 1 1 32 8 32 8 1024 8 i 16384 16w
008: 0 5 0 0 2 1 32 8 32 8 1024 8 i 16384 16w
009: 0 7 0 0 3 1 32 8 32 8 1024 8 i 16384 16w
010: 0 9 0 1 4 1 32 8 32 8 1024 8 i 16384 16w
011: 0 11 0 1 5 1 32 8 32 8 1024 8 i 16384 16w
[ 0] American Megatrends Inc.
[ 1] 2413
[ 2] 02/02/2024
[ 3] ASUS
[ 4] System Product Name
[ 5] System Version
[ 6] S---e---e---l---m---
[ 7] SKU
[ 8] To be filled by O.E.M.
[ 9] ASUSTeK COMPUTER INC.
[10] ROG STRIX B650E-I GAMING WIFI
[11] Rev 1.xx
[12] 2---2---1---0--
[13] Number Of Devices:2\Maximum Capacity:134217728 kilobytes
[14] DIMM 1\P0 CHANNEL A
[15] DIMM 1\P0 CHANNEL B
[16]
[17]
[18] G Skill Intl
[19] G Skill Intl
[20]
[21]
[22] F5-8000J4048F24G
[23] F5-8000J4048F24G
[24]
[25]
Zen UMC [14F0]
Controller #0 Quad Channel
Bus Rate 4000 MHz Bus Speed 4046 MHz DDR5 Speed 8092 MT/s
Cha CL RCDr RCDw RP RAS RC RRDs RRDl FAW WTRs WTRl WR clRR clWW
#0 40 48 48 48 127 192 8 16 41 10 40 120 14 34
#1 40 48 48 48 127 192 8 16 41 10 40 120 14 34
#2 40 48 48 48 127 192 8 16 41 10 40 120 14 34
#3 40 48 48 48 127 192 8 16 41 10 40 120 14 34
CWL RTP RdWr WrRd scWW sdWW ddWW scRR sdRR ddRR drRR drWW drWR drRRD
#0 38 24 25 7 2 15 15 2 14 14 0 0 0 0
#1 38 24 24 7 2 15 15 2 14 14 0 0 0 0
#2 38 24 25 7 2 15 15 2 14 14 0 0 0 0
#3 38 24 25 7 2 15 15 2 14 14 0 0 0 0
REFI RFC1 RFC2 RFCsb RCPB RPPB BGS:Alt Ban Page CKE CMD GDM ECC
#0 15554 312 192 758 0 0 ON OFF R0W0 0 6 1T ON 0
#1 15554 312 192 758 0 0 ON OFF R0W0 0 6 1T ON 0
#2 15554 312 192 758 0 0 ON OFF R0W0 0 6 1T ON 0
#3 15554 312 192 758 0 0 ON OFF R0W0 0 6 1T ON 0
MRD:PDA MOD:PDA WRMPR STAG PDM RDDATA WRD WRL RDL XS XP CPDED
#0 56 0 56 0 24 7 0:F:0 28 6 26 0 1676 30 4
#1 56 0 56 0 24 7 0:F:0 28 6 26 0 1676 30 4
#2 56 0 56 0 24 7 0:F:0 28 6 26 2 1676 30 4
#3 56 0 56 0 24 7 0:F:0 28 6 26 2 1676 30 4
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 32 1 131072 1024 32768 F5-8000J4048F24G
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 32 1 131072 1024 32768 F5-8000J4048F24G
DIMM Geometry for channel #2
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 32 1 131072 1024 32768 F5-8000J4048F24G
DIMM Geometry for channel #3
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 32 1 131072 1024 32768 F5-8000J4048F24G
Linux:
|- Release [6.7.8-zen1-1-zen]
|- Version [#1 ZEN SMP PREEMPT_DYNAMIC Sun, 03 Mar 2024 00:30:23 +0000]
|- Machine [x86_64]
Memory:
|- Total RAM 46974936 KB
|- Shared RAM 118264 KB
|- Free RAM 25178976 KB
|- Buffer RAM 254336 KB
|- Total High 0 KB
|- Free High 0 KB
Clock Source < corefreq_tsc>
CPU-Freq driver [ amd-pstate-epp]
Governor [ Missing]
CPU-Idle driver [ acpi_idle]
|- Idle Limit [ C3]
|- State POLL C1 C2 C3
|- CPUIDLE ACPI FF ACPI IO ACPI IO
|- Power -1 0 0 0
|- Latency 0 1 18 350
|- Residency 0 2 36 700
CPU Freq(MHz) VID Vcore TMP(C) Accumulator Energy(J) Power(W)
000 1030.77 200 1.2500 0 000000000000259515 3.959884644 3.959884644
001 1220.56 200 1.2500 0 000000000000269040 4.105224609 4.105224609
002 1474.28 200 1.2500 0 000000000000275232 4.199707031 4.199707031
003 1564.93 200 1.2500 0 000000000000338725 5.168533325 5.168533325
004 1235.66 200 1.2500 0 000000000000260423 3.973739624 3.973739624
005 1442.03 200 1.2500 0 000000000000323952 4.943115234 4.943115234
006 1662.86 200 1.2500 0 000000000000000000 0.000000000 0.000000000
007 1733.71 200 1.2500 0 000000000000000000 0.000000000 0.000000000
008 855.90 200 1.2500 0 000000000000000000 0.000000000 0.000000000
009 1628.66 200 1.2500 0 000000000000000000 0.000000000 0.000000000
010 1404.28 200 1.2500 0 000000000000000000 0.000000000 0.000000000
011 1659.44 200 1.2500 0 000000000000000000 0.000000000 0.000000000
Package[0] Cores Uncore Memory Platform
Energy(J): 43.076538086 26.350204468 0.000000000 0.000000000 0.000000000
Power(W) : 43.076538086 26.350204468 0.000000000 0.000000000 0.000000000
CPU IPS IPC CPI
000 0.216791/s 1.040506/c 0.961071/i
001 0.213990/s 1.061428/c 0.942127/i
002 0.237844/s 1.051879/c 0.950680/i
003 2.133788/s 3.512140/c 0.284727/i
004 0.374876/s 1.294412/c 0.772552/i
005 0.589201/s 1.675322/c 0.596900/i
006 0.192485/s 0.869787/c 1.149707/i
007 0.508838/s 1.171443/c 0.853648/i
008 0.249772/s 0.991509/c 1.008564/i
009 0.216775/s 0.702998/c 1.422478/i
010 0.326184/s 0.998303/c 1.001700/i
011 0.323157/s 1.060911/c 0.942586/i
CPU Freq(MHz) VID Min Vcore Max
000 691.00 203 0.7313 1.2688 1.5063
001 872.02 203 0.7313 1.2688 1.5063
002 835.70 203 0.7313 1.2688 1.5063
003 2357.92 203 0.7313 1.2688 1.5063
004 881.62 203 0.7313 1.2688 1.5063
005 1108.82 203 0.7313 1.2688 1.5063
006 978.78 203 0.7313 1.2688 1.5063
007 1751.76 203 0.7313 1.2688 1.5063
008 1038.24 203 0.7313 1.2688 1.5063
009 861.55 203 0.7313 1.2688 1.5063
010 880.22 203 0.7313 1.2688 1.5063
011 1029.20 203 0.7313 1.2688 1.4500
CPU Freq(MHz) Accumulator Min Energy(J) Max Min Power(W) Max
000 834.44 000000000000223024 1.52 3.40 11.28 1.52 3.40 11.28
001 822.34 000000000000313695 1.84 4.79 10.66 1.84 4.79 10.66
002 975.69 000000000000237530 1.74 3.62 9.78 1.74 3.62 9.78
003 1100.89 000000000000300436 2.23 4.58 10.04 2.23 4.58 10.04
004 3266.18 000000000000462533 2.22 7.06 10.17 2.22 7.06 10.17
005 829.89 000000000000272736 1.90 4.16 11.46 1.90 4.16 11.46
006 723.73 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
007 1412.94 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
008 908.46 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
009 1327.80 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
010 659.88 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
011 1062.34 000000000000000000 0.00 0.00 0.00 0.00 0.00 0.00
Energy(J) Package[0] Cores Uncore Memory
29.45 38.12 74.32 9.40 27.62 57.78 0.00 0.00 0.00 0.00 0.00 0.00
Power(W)
29.45 38.12 74.32 9.40 27.62 57.78 0.00 0.00 0.00 0.00 0.00 0.00
CPU Freq(MHz) Ratio Turbo C0(%) C1(%) C3(%) C6(%) C7(%) Min TMP:TS Max
000 1373.05 (13.57) 31.56 29.88 70.12 0.00 0.00 0.00 0 / 0:0 / 0
001 978.91 ( 9.68) 22.50 21.98 78.02 0.00 0.00 0.00 0 / 0:0 / 0
002 913.51 ( 9.03) 21.00 20.29 79.71 0.00 0.00 0.00 0 / 0:0 / 0
003 1242.21 (12.28) 28.55 26.74 73.26 0.00 0.00 0.00 0 / 0:0 / 0
004 1988.11 (19.65) 45.70 41.56 58.44 0.00 0.00 0.00 0 / 0:0 / 0
005 1182.26 (11.69) 27.18 25.73 74.27 0.00 0.00 0.00 0 / 0:0 / 0
006 1007.47 ( 9.96) 23.16 21.97 78.03 0.00 0.00 0.00 0 / 0:0 / 0
007 1017.24 (10.05) 23.38 22.50 77.50 0.00 0.00 0.00 0 / 0:0 / 0
008 1181.07 (11.67) 27.15 26.02 73.98 0.00 0.00 0.00 0 / 0:0 / 0
009 1155.23 (11.42) 26.56 25.42 74.58 0.00 0.00 0.00 0 / 0:0 / 0
010 500.60 ( 4.95) 11.51 11.45 88.55 0.00 0.00 0.00 0 / 0:0 / 0
011 825.14 ( 8.16) 18.97 18.27 81.73 0.00 0.00 0.00 0 / 0:0 / 0
Averages: Turbo C0(%) C1(%) C3(%) C6(%) C7(%) TjMax: Pkg:
25.60 24.32 75.68 0.00 0.00 0.00 0 C 0 CThank you for the output. That Ryzen series is really filling the gap with Intel: all ISA and Features are available (beside oldish legacies)
amd_pstate might be compiled as static
Try the below boot parameters
modprobe.blacklist=acpi_cpufreq amd_pstate.shared_mem=0 amd_pstate=disable idle=haltTemperature is not showing. That's an issue. I'm searching for thermal registers and will come back with code for testings.
EUA
commented
4 months ago With custom kernel boot parameters and again custom corefreqk kernel module parameters, there is an improvement.
Now CoreFreq reports something on C2-C3 column. But I believe, it should be need CC6 state indeed.
cyring
commented
4 months ago it should be need CC6
Using short key k or Menu > Kernel to open the Kernel window; next, select Idle limit to C6
Edit: prerequisites are CoreFreq well registered as CPU-Idle
Edit: I forgot to add a parameter to make limit permanent. I will add it soon. Meanwhile you can still use the UI to switch C-State limit as will.
cyring
commented
4 months ago Btw can you disable any SPREAD SPECTRUM in your BIOS ?
The expected effect is that the Base Clock should estimate to 100,000,000 Hz.
You should get an estimation of DRAM to 8000 MT/s
cyring
commented
4 months ago @EUA
Now CoreFreq reports something on C2-C3 column. But I believe, it should be need CC6 state indeed.
Edit: I forgot to add a parameter to make limit permanent. I will add it soon. Meanwhile you can still use the UI to switch C-State limit as will.
I forgot I already made it available through the parameter Override_SubCstate
For example, looking at your Sub C-State (See "Performance Monitoring" window)
|- MONITOR/MWAIT
|- State index: #0 #1 #2 #3 #4 #5 #6 #7
|- Sub C-State: 1 1 0 0 0 0 0 0 If your want to make CC6 as a startup limit, you will set a 1 at each index up to the 6th and pad with 0 up to the last 8th
insmod build/corefreqk.ko Register_ClockSource=1 Register_Governor=1 \
Register_CPU_Idle=1 Register_CPU_Freq=1 \
Override_SubCstate="1,1,1,1,1,1,0,0"As a result, you will get such override
|- MONITOR/MWAIT
|- State index: #0 #1 #2 #3 #4 #5 #6 #7
|- Sub C-State: 1 1 1 1 1 1 0 0 And the kernel Idle Limit as the following
Clock Source < corefreq_tsc>
CPU-Freq driver [ corefreqk-perf]
Governor [ corefreq-policy]
CPU-Idle driver [ corefreqk-idle]
|- Idle Limit < C6>
|- State POLL C1 C2 C3 C4 C5 C6
|- CPUIDLE ZEN-C1 ZEN-C2 ZEN-C3 ZEN-C4 ZEN-C5 ZEN-C6
|- Power -1 0 0 0 0 0 0
|- Latency 0 1 20 40 60 80 100
|- Residency 0 2 40 80 120 160 200 Consequently Monitoring will start using CC6:
EUA
commented
4 months ago Yup. Now it's looks better. Thanks.
cyring
commented
4 months ago EUA
commented
4 months ago Here is the registers you asking for:
[root@Ryzen CoreFreq]# ./zencli smu 0x59800
[0x00059800] READ(smu) = 0x822b0000 (2183856128)
60 56 52 48 44 40 36 32 28 24 20 16 12 08 04 00
0000 0000 0000 0000 0000 0000 0000 0000 1000 0010 0010 1011 0000 0000 0000 0000
[root@Ryzen CoreFreq]# ./zencli smu 0x59954
[0x00059954] READ(smu) = 0x00000000 (0)
60 56 52 48 44 40 36 32 28 24 20 16 12 08 04 00
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
[root@Ryzen CoreFreq]# ./zencli smu 0x59B08
[0x00059b08] READ(smu) = 0x00000000 (0)
60 56 52 48 44 40 36 32 28 24 20 16 12 08 04 00
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
[root@Ryzen CoreFreq]# @EUA
Can you please pull develop branch and test temperature ?
Edit: Should also be fixed the UMC reduction to two DIMMs
Please refresh corefreq-cli -s -n -C 1 -n -c 1 -n -k -n -B -n -M
EUA
commented
4 months ago Output from develop branch ;
Processor [AMD Ryzen 5 8600G w/ Radeon 760M Graphics]
|- Architecture [Zen4/Hawk Point]
|- Vendor ID [AuthenticAMD]
|- Microcode [0x0a705203]
|- Signature [ AF_75]
|- Stepping [ 2]
|- Online CPU [ 12/ 12]
|- Base Clock [101.171]
|- Frequency (MHz) Ratio
Min 1618.74 < 16 >
Max 4350.36 < 43 >
|- Factory [100.000]
4300 [ 43 ]
|- Performance
|- P-State
TGT 4350.36 < 43 >
|- Turbo Boost [ UNLOCK]
XFR 5058.56 [ 50 ]
CPB 5058.56 [ 50 ]
1C 2225.77 < 22 >
2C 1618.74 < 16 >
|- Uncore [ LOCK]
CLK 2023.42 [ 20 ]
MEM 4046.85 [ 40 ]
Instruction Set Extensions
|- 3DNow!/Ext [N/N] ADX [Y] AES [Y] AVX/AVX2 [Y/Y]
|- AVX512-F [Y] AVX512-DQ [Y] AVX512-IFMA [Y] AVX512-PF [N]
|- AVX512-ER [N] AVX512-CD [Y] AVX512-BW [Y] AVX512-VL [Y]
|- AVX512-VBMI [Y] AVX512-VBMI2 [Y] AVX512-VNNI [Y] AVX512-ALG [Y]
|- AVX512-VPOP [Y] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N]
|- AVX512-BF16 [Y] AVX-VNNI-VEX [N] AVX-FP128 [N] AVX-FP256 [Y]
|- BMI1/BMI2 [Y/Y] CLWB [Y] CLFLUSH [Y] CLFLUSH-OPT [Y]
|- CLAC-STAC [Y] CMOV [Y] CMPXCHG8B [Y] CMPXCHG16B [Y]
|- F16C [Y] FPU [Y] FXSR [Y] LAHF-SAHF [Y]
|- MMX/Ext [Y/Y] MON/MWAITX [Y/Y] MOVBE [Y] PCLMULQDQ [Y]
|- POPCNT [Y] RDRAND [Y] RDSEED [Y] RDTSCP [Y]
|- SEP [Y] SHA [Y] SSE [Y] SSE2 [Y]
|- SSE3 [Y] SSSE3 [Y] SSE4.1/4A [Y/Y] SSE4.2 [Y]
|- SERIALIZE [N] SYSCALL [Y] RDPID [Y] UMIP [Y]
|- VAES [Y] VPCLMULQDQ [Y] PREFETCH/W [Y] LZCNT [Y]
Features
|- 1 GB Pages Support 1GB-PAGES [Capable]
|- 100 MHz multiplier Control 100MHzSteps [Missing]
|- Advanced Configuration & Power Interface ACPI [Capable]
|- Advanced Programmable Interrupt Controller APIC [Capable]
|- Advanced Virtual Interrupt Controller AVIC [Capable]
|- APIC Timer Invariance ARAT [Capable]
|- LOCK prefix to read CR8 AltMov [Capable]
|- Clear Zero Instruction CLZERO [Capable]
|- Core Multi-Processing CMP Legacy [Capable]
|- L1 Data Cache Context ID CNXT-ID [Missing]
|- Collaborative Processor Performance Control CPPC [Capable]
|- Direct Cache Access DCA [Missing]
|- Debugging Extension DE [Capable]
|- Debug Store & Precise Event Based Sampling DS, PEBS [Missing]
|- CPL Qualified Debug Store DS-CPL [Missing]
|- 64-Bit Debug Store DTES64 [Missing]
|- Fast Short REP MOVSB FSRM [Capable]
|- Fast-String Operation ERMS [Capable]
|- Fused Multiply Add FMA4 [Missing]
|- Fused Multiply Add FMA [Capable]
|- Hardware Lock Elision HLE [Missing]
|- Hyper-Threading Technology HTT [Capable]
|- Hardware P-state control HwP [Capable]
|- Instruction Based Sampling IBS [Capable]
|- Instruction INVLPGB INVLPGB [Missing]
|- Instruction INVPCID INVPCID [Capable]
|- Long Mode 64 bits IA64 | LM [Capable]
|- LightWeight Profiling LWP [Missing]
|- Memory Bandwidth Enforcement MBE [Capable]
|- Machine-Check Architecture MCA [Capable]
|- Instruction MCOMMIT MCOMMIT [Missing]
|- Model Specific Registers MSR [Capable]
|- Memory Type Range Registers MTRR [Capable]
|- No-Execute Page Protection NX [Capable]
|- OS-Enabled Ext. State Management OSXSAVE [Capable]
|- OS Visible Work-around OSVW [Capable]
|- Physical Address Extension PAE [Capable]
|- Page Attribute Table PAT [Capable]
|- Pending Break Enable PBE [Missing]
|- Process Context Identifiers PCID [Missing]
|- Perfmon and Debug Capability PDCM [Missing]
|- Page Global Enable PGE [Capable]
|- Page Size Extension PSE [Capable]
|- 36-bit Page Size Extension PSE36 [Capable]
|- Processor Serial Number PSN [Missing]
|- Resource Director Technology/PQE RDT-A [Capable]
|- Resource Director Technology/PQM RDT-M [Capable]
|- Read Processor Register at User level RDPRU [Capable]
|- Restricted Transactional Memory RTM [Missing]
|- Safer Mode Extensions SMX [Missing]
|- Self-Snoop SS [Missing]
|- Supervisor-Mode Access Prevention SMAP [Capable]
|- Supervisor-Mode Execution Prevention SMEP [Capable]
|- Trailing Bit Manipulation TBM [Missing]
|- Translation Cache Extension TCE [Capable]
|- Time Stamp Counter TSC [Invariant]
|- Time Stamp Counter Deadline TSC-DEADLINE [Missing]
|- TSX Force Abort MSR Register TSX-ABORT [Missing]
|- TSX Suspend Load Address Tracking TSX-LDTRK [Missing]
|- User-Mode Instruction Prevention UMIP [Capable]
|- Virtual Mode Extension VME [Capable]
|- Virtual Machine Extensions VMX [Missing]
|- Write Back & Do Not Invalidate Cache WBNOINVD [Capable]
|- Extended xAPIC Support x2APIC [ xAPIC]
|- AVIC controller for x2APIC x2AVIC [Capable]
|- XSAVE/XSTOR States XSAVE [Capable]
|- xTPR Update Control xTPR [Missing]
|- Extended Operation Support XOP [Missing]
Mitigation mechanisms
|- Indirect Branch Restricted Speculation IBRS [Capable]
|- IBRS Always-On preferred by processor [ Unable]
|- IBRS preferred over software solution [Capable]
|- IBRS provides same speculation limits [Capable]
|- Indirect Branch Prediction Barrier IBPB [Capable]
|- Single Thread Indirect Branch Predictor STIBP [ Enable]
|- Speculative Store Bypass Disable SSBD [Capable]
|- SSBD use VIRT_SPEC_CTRL register [ Unable]
|- SSBD not needed on this processor [ Unable]
|- No Branch Type Confusion BTC_NO [ Unable]
|- BTC on Non-Branch instruction BTC-NOBR [Capable]
|- Limited Early Redirect Window AGENPICK [ Unable]
|- Arch - No Fast Predictive Store Forwarding PSFD [Capable]
|- Arch - Enhanced Predictive Store Forwarding EPSF [Capable]
|- Arch - Cross Processor Information Leak XPROC_LEAK [ Unable]
Security Features
|- CET Shadow Stack features CET-SS [Capable]
|- Secure Init and Jump with Attestation SKINIT [Capable]
|- Secure Encrypted Virtualization SEV [Missing]
|- SEV - Encrypted State SEV-ES [Missing]
|- SEV - Secure Nested Paging SEV-SNP [Missing]
|- Guest Mode Execute Trap GMET [Capable]
|- Supervisor Shadow Stack SSS [Capable]
|- VM Permission Levels VMPL [Missing]
|- VMPL Supervisor Shadow Stack VMPL-SSS [Missing]
|- Secure Memory Encryption SME [Capable]
|- Transparent SME TSME [ Enable]
|- Secure Multi-Key Memory Encryption SME-MK [Missing]
|- DRAM Data Scrambling Scrambler [ Enable]
Technologies
|- Instruction Cache Unit
|- L1 IP Prefetcher L1 HW IP < ON>
|- Data Cache Unit
|- L1 Prefetcher L1 HW < ON>
|- Cache Prefetchers
|- L2 Prefetcher L2 HW < ON>
|- L1 Stride Prefetcher L1 Stride < ON>
|- L1 Region Prefetcher L1 Region < ON>
|- L1 Burst Prefetch Mode L1 Burst < ON>
|- L2 Stream HW Prefetcher L2 Stream < ON>
|- L2 Up/Down Prefetcher L2 Up/Down < ON>
|- System Management Mode SMM-Lock [ ON]
|- Simultaneous Multithreading SMT [ ON]
|- PowerNow! CnQ [ ON]
|- Core C-States CCx [ ON]
|- Core Performance Boost CPB < ON>
|- Watchdog Timer WDT < ON>
|- Virtualization SVM [ ON]
|- I/O MMU AMD-V [ ON]
|- Version [ 0.1]
|- Hypervisor [OFF]
|- Vendor ID [ N/A]
Performance Monitoring
|- Version PM [ 2]
|- Counters: General Fixed
| { 6, 6, 4 } x 48 bits 3 x 64 bits
|- Enhanced Halt State C1E <OFF>
|- C2 UnDemotion C2U < ON>
|- C3 UnDemotion C3U < ON>
|- Core C6 State CC6 < ON>
|- Package C6 State PC6 < ON>
|- Legacy Frequency ID control FID [OFF]
|- Legacy Voltage ID control VID [OFF]
|- P-State Hardware Coordination Feedback MPERF/APERF [ ON]
|- Core C-States
|- C-States Base Address BAR [ 0x413 ]
|- ACPI Processor C-States _CST [ 3]
|- MONITOR/MWAIT
|- State index: #0 #1 #2 #3 #4 #5 #6 #7
|- Sub C-State: 1 1 1 1 1 1 0 0
|- Monitor-Mwait Extensions EMX [Capable]
|- Interrupt Break-Event IBE [Capable]
|- Core Cycles [Capable]
|- Instructions Retired [Capable]
|- Reference Cycles [Capable]
|- Last Level Cache References [Capable]
|- Global Time Stamp Counter [Missing]
|- Data Fabric Performance Counter [Capable]
|- Core Performance Counter [Capable]
|- Processor Performance Control _PCT [ Enable]
|- Performance Supported States _PSS [ 3]
|- Performance Present Capabilities _PPC [ 0]
|- Continuous Performance Control _CPC [Missing]
Power, Current & Thermal
|- Temperature Offset:Junction TjMax [ 0: 0 C]
|- CPPC Energy Preference EPP [Capable]
|- Digital Thermal Sensor DTS [Capable]
|- Power Limit Notification PLN [Missing]
|- Package Thermal Management PTM [Missing]
|- Thermal Monitor 1 TTP [ Enable]
|- Thermal Monitor 2 HTC [ Enable]
|- Thermal Design Power TDP [Missing]
|- Minimum Power Min [Missing]
|- Maximum Power Max [Missing]
|- Thermal Design Power Package [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 0 ns]
|- Power Limit PL2 [ 0 W]
|- Time Window TW2 [ 0 ns]
|- Thermal Design Power Core [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 0 ns]
|- Thermal Design Power Uncore [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 0 ns]
|- Thermal Design Power DRAM [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 0 ns]
|- Thermal Design Power Platform [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 0 ns]
|- Power Limit PL2 [ 0 W]
|- Time Window TW2 [ 0 ns]
|- Package Power Tracking PPT [Missing]
|- Electrical Design Current EDC [Missing]
|- Thermal Design Current TDC [Missing]
|- Core Thermal Point
|- Package Thermal Point
|- Thermal Monitor Trip Limit [ 115 C]
|- HTC Temperature Limit Limit [ 127 C]
|- HTC Temperature Hysteresis Threshold [ 2 C]
|- Units
|- Power watt [ 0.125000000]
|- Energy joule [ 0.000015259]
|- Window second [ 0.000976562]
CPU Freq(MHz) VID Vcore TMP(C) Accumulator Energy(J) Power(W)
000 1409.89 208 1.3000 0 000000000000287526 4.387298584 4.387298584
001 1064.18 208 1.3000 0 000000000000291462 4.447357178 4.447357178
002 715.29 208 1.3000 0 000000000000208965 3.188552856 3.188552856
003 1544.10 208 1.3000 0 000000000000347671 5.305038452 5.305038452
004 1855.75 208 1.3000 0 000000000000303876 4.636779785 4.636779785
005 1266.17 208 1.3000 0 000000000000234158 3.572967529 3.572967529
006 1295.98 208 1.3000 0 000000000000000000 0.000000000 0.000000000
007 1094.05 207 1.2938 0 000000000000000000 0.000000000 0.000000000
008 781.02 207 1.2938 0 000000000000000000 0.000000000 0.000000000
009 1123.45 207 1.2938 0 000000000000000000 0.000000000 0.000000000
010 592.60 207 1.2938 0 000000000000000000 0.000000000 0.000000000
011 709.02 207 1.2938 0 000000000000000000 0.000000000 0.000000000
Package[0] Cores Uncore Memory Platform
Energy(J): 36.467819214 20.191711426 0.000000000 0.000000000 0.000000000
Power(W) : 36.467819214 20.191711426 0.000000000 0.000000000 0.000000000
CPU Freq(MHz) Ratio Turbo C0(%) C1(%) C3(%) C6(%) C7(%) Min TMP:TS Max
000 1409.89 (13.94) 32.41 30.99 69.01 0.00 0.00 0.00 0 / 0:0 / 0
001 1064.18 (10.52) 24.46 23.57 76.43 0.00 0.00 0.00 0 / 0:0 / 0
002 715.29 ( 7.07) 16.44 17.45 82.55 0.00 0.00 0.00 0 / 0:0 / 0
003 1544.10 (15.26) 35.49 33.82 66.18 0.00 0.00 0.00 0 / 0:0 / 0
004 1855.75 (18.34) 42.66 40.30 59.70 0.00 0.00 0.00 0 / 0:0 / 0
005 1266.17 (12.51) 29.10 28.23 71.77 0.00 0.00 0.00 0 / 0:0 / 0
006 1295.98 (12.81) 29.79 28.92 71.08 0.00 0.00 0.00 0 / 0:0 / 0
007 1094.05 (10.81) 25.15 24.64 75.36 0.00 0.00 0.00 0 / 0:0 / 0
008 781.02 ( 7.72) 17.95 18.22 81.78 0.00 0.00 0.00 0 / 0:0 / 0
009 1123.45 (11.10) 25.82 25.12 74.88 0.00 0.00 0.00 0 / 0:0 / 0
010 592.60 ( 5.86) 13.62 13.92 86.08 0.00 0.00 0.00 0 / 0:0 / 0
011 709.02 ( 7.01) 16.30 16.65 83.35 0.00 0.00 0.00 0 / 0:0 / 0
Averages: Turbo C0(%) C1(%) C3(%) C6(%) C7(%) TjMax: Pkg:
25.77 25.15 74.85 0.00 0.00 0.00 0 C 0 C
Linux:
|- Release [6.8.1-zen1-1-zen]
|- Version [#1 ZEN SMP PREEMPT_DYNAMIC Sat, 16 Mar 2024 17:15:23 +0000]
|- Machine [x86_64]
Memory:
|- Total RAM 46973540 KB
|- Shared RAM 100140 KB
|- Free RAM 25660812 KB
|- Buffer RAM 297008 KB
|- Total High 0 KB
|- Free High 0 KB
Clock Source < corefreq_tsc>
CPU-Freq driver [ corefreqk-perf]
Governor [ corefreq-policy]
CPU-Idle driver [ Missing]
|- Idle Limit [ N/A]
[ 0] American Megatrends Inc.
[ 1] 2413
[ 2] 02/02/2024
[ 3] ASUS
[ 4] System Product Name
[ 5] System Version
[ 6] S---e---e---l---m---
[ 7] SKU
[ 8] To be filled by O.E.M.
[ 9] ASUSTeK COMPUTER INC.
[10] ROG STRIX B650E-I GAMING WIFI
[11] Rev 1.xx
[12] 2---2---1---0--
[13] Number Of Devices:2\Maximum Capacity:134217728 kilobytes
[14] DIMM 1\P0 CHANNEL A
[15] DIMM 1\P0 CHANNEL B
[16]
[17]
[18] G Skill Intl
[19] G Skill Intl
[20]
[21]
[22] F5-8000J4048F24G
[23] F5-8000J4048F24G
[24]
[25]
Zen UMC [14F0]
Controller #0 Quad Channel
Bus Rate 4000 MHz Bus Speed 4046 MHz DDR5 Speed 8092 MT/s
Cha CL RCDr RCDw RP RAS RC RRDs RRDl FAW WTRs WTRl WR clRR clWW
#0 40 48 48 48 127 192 8 16 41 10 40 120 14 34
#1 40 48 48 48 127 192 8 16 41 10 40 120 14 34
#2 40 48 48 48 127 192 8 16 41 10 40 120 14 34
#3 40 48 48 48 127 192 8 16 41 10 40 120 14 34
CWL RTP RdWr WrRd scWW sdWW ddWW scRR sdRR ddRR drRR drWW drWR drRRD
#0 38 24 25 7 2 15 15 2 14 14 0 0 0 0
#1 38 24 24 7 2 15 15 2 14 14 0 0 0 0
#2 38 24 25 7 2 15 15 2 14 14 0 0 0 0
#3 38 24 25 7 2 15 15 2 14 14 0 0 0 0
REFI RFC1 RFC2 RFCsb RCPB RPPB BGS:Alt Ban Page CKE CMD GDM ECC
#0 15554 312 192 758 0 0 ON OFF R0W0 0 6 1T ON 0
#1 15554 312 192 758 0 0 ON OFF R0W0 0 6 1T ON 0
#2 15554 312 192 758 0 0 ON OFF R0W0 0 6 1T ON 0
#3 15554 312 192 758 0 0 ON OFF R0W0 0 6 1T ON 0
MRD:PDA MOD:PDA WRMPR STAG PDM RDDATA WRD WRL RDL XS XP CPDED
#0 56 0 56 0 24 7 0:F:0 28 6 26 0 1676 30 4
#1 56 0 56 0 24 7 0:F:0 28 6 26 0 1676 30 4
#2 56 0 56 0 24 7 0:F:0 28 6 26 2 1676 30 4
#3 56 0 56 0 24 7 0:F:0 28 6 26 2 1676 30 4
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 32 1 131072 1024 32768 F5-8000J4048F24G
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 32 1 131072 1024 32768 F5-8000J4048F24G
DIMM Geometry for channel #2
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 32 1 131072 1024 32768 F5-8000J4048F24G
DIMM Geometry for channel #3
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 32 1 131072 1024 32768 F5-8000J4048F24GAs dump with
zencli smu 0x59800
I was expecting to read temperature.
But also 2 DRAM sticks.
Do you confirm building/running latest commits ?
EUA
commented
4 months ago I did;
git branch develop
git pull
makeOnly kernel module rebuilt. I am not git guru but, I think this is what should I need to do... Don't know how to verify it.
Than insmod as you write at top... Don't know if I am able to switch properly but... Something pulled from git.
I have 2 Ram slot on my MB and both of them used with 24GB Sticks.
cyring
commented
4 months ago I think I have a digit mistake in register address. Can you edit this header file at that line: https://github.com/cyring/CoreFreq/blob/87344fae6395c7d3d5dd6b7b0876a6ee3aae413d/x86_64/amd_reg.h#L208
and replace code with this one:
#define SMU_AMD_THM_TCTL_CCD_REGISTER_F19H_61H \
(SMU_AMD_THM_TCTL_REGISTER_F17H + 0x300)Edit this other header file: https://github.com/cyring/CoreFreq/blob/87344fae6395c7d3d5dd6b7b0876a6ee3aae413d/x86_64/corefreqk.h#L11869
and replace function pointer as bellow:
.Query = Query_AMD_F19h_61h_PerClusterNext please rebuild all
make clean
makeAnd reload all for temperature testing (make sure to unload before loading driver again)
Thank you
EDIT: For DIMM geometry, can you also peek those addresses
## Prior Zen4
./zencli smu 0x50030
./zencli smu 0x50034
./zencli smu 0x50038
./zencli smu 0x5003C
## Since Zen4
./zencli smu 0x50040
./zencli smu 0x50044
./zencli smu 0x50048
./zencli smu 0x5004CReplaced the lines as you indicated. Still no core temps appears on main screen.
./zencli smu 0x50030
./zencli smu 0x50034
./zencli smu 0x50038
./zencli smu 0x5003C
## Since Zen4
./zencli smu 0x50040
./zencli smu 0x50044
./zencli smu 0x50048
./zencli smu 0x5004C
[0x00050030] READ(smu) = 0x00000000 (0)
60 56 52 48 44 40 36 32 28 24 20 16 12 08 04 00
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
[0x00050034] READ(smu) = 0x00000000 (0)
60 56 52 48 44 40 36 32 28 24 20 16 12 08 04 00
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
[0x00050038] READ(smu) = 0x00fffffe (16777214)
60 56 52 48 44 40 36 32 28 24 20 16 12 08 04 00
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1111 1110
[0x0005003c] READ(smu) = 0x00000000 (0)
60 56 52 48 44 40 36 32 28 24 20 16 12 08 04 00
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
[0x00050040] READ(smu) = 0x00150508 (1377544)
60 56 52 48 44 40 36 32 28 24 20 16 12 08 04 00
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0101 0000 0101 0000 1000
[0x00050044] READ(smu) = 0x00150508 (1377544)
60 56 52 48 44 40 36 32 28 24 20 16 12 08 04 00
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0101 0000 0101 0000 1000
[0x00050048] READ(smu) = 0x0025070c (2426636)
60 56 52 48 44 40 36 32 28 24 20 16 12 08 04 00
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0010 0101 0000 0111 0000 1100
[0x0005004c] READ(smu) = 0x00150508 (1377544)
60 56 52 48 44 40 36 32 28 24 20 16 12 08 04 00
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0101 0000 0101 0000 1000I don't know what this SMU outputs means but... I definitely sure about that, at least, one of my sticks is placed at other slot and my Rams are 24GB. Looks like some electronic info at chips do not comply with reality. :smile:
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 32 1 131072 1024 32768 F5-8000J4048F24G
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 32 1 131072 1024 32768 F5-8000J4048F24G
DIMM Geometry for channel #2
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 32 1 131072 1024 32768 F5-8000J4048F24G
DIMM Geometry for channel #3
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 32 1 131072 1024 32768 F5-8000J4048F24G
@EUA
Replaced the lines as you indicated. Still no core temps appears on main screen.
So it appears that fix is working for EPYC/Genoa but fails on yours and 7950X
I don't know what this SMU outputs means
I'm making a page to debug new DIMMs
cyring
commented
4 months ago @EUA
Can you load the k10temp module and show the temperature output from sensors command ?
EUA
commented
4 months ago Of-course I am.
Adapter: PCI adapter
Tctl: +82.9°CUnfortunately, zenpower does not work anymore. With detailed info about Zen CPU's, might be you can fetch Voltage and Current info from SVI and revive the project as your fork...
cyring
commented
4 months ago That's the odd thing: Making use of the same SMU thermal address as the one mentioned in k10temp source code and not reading a temperature value !
Tctl Register has to be at 0x59800 + 0x308:
zencli smu 0x59B08If +82.9°C was not your current CPU temperature, it means sensors returned a garbage value.
cyring
commented
4 months ago Unfortunately, zenpower does not work anymore. With detailed info about Zen CPU's, might be you can fetch Voltage and Current info from SVI and revive the project as your fork...
corefreq-cli -jcan output data in JSON, including voltage, power, temp
EUA
commented
4 months ago And k10temp is actually reading from the die temp. So it's reading perfectly correct while I am mining crypto with my CPU right now :) nct6799-isa-0290 is also reporting it as : TSI0_TEMP: +81.6°C right now.
Unfortunately, 8000G series has ultra thick IHS, glued with low grade thermal glue. (really a big shame for AMD!) Just altering thermal paste with PTM7950 or a liquid metal reduces temps up to 25C degree (of-course with AIO setup). I am planning to delid it soon, when my PTM7950 thermal pad comes from AliExpress. So might be my fan could gonna holiday even if I am torturing the CPU with cryptos...
zencli smu 0x59B08 returns all zeros, nothing more. So might be zencli not working OR, do you sure about if correct base address is really 0x59800 for my CPU?
While corefreq-cli -j can return those data, but AFAIK all linux users will definitely prefer to see it on lm-sensors directly. Not from another program. So we could move that value into Gnome shell, with freon extension. Think about it. I don't think if it's hard to do while you have already the working code... Probably req. just adding some numbers into header file and viola...
cyring
commented
4 months ago @EUA
OR, do you sure about if correct base address is really 0x59800 for my CPU?
Brillant suggestion you have.
Looking closer into function k10temp_get_ccd_support which loops 8 times, starting from 0x59800 + 0x308, adding index multiplied by 4 at each step, and attempting a temperature read if bit 11 is raised.
So can you please read this range of the 7 remaining addresses ?
zencli smu 0x59B0C
zencli smu 0x59B10
zencli smu 0x59B14
zencli smu 0x59B18
zencli smu 0x59B1C
zencli smu 0x59B20
zencli smu 0x59B24@EUA Hello. Not sure if you were notified about above zencli readings ?
EUA
commented
4 months ago @EUA
OR, do you sure about if correct base address is really 0x59800 for my CPU?
Brillant suggestion you have.
Yup. Have some natural gift on beta testing. :) I have busy with soldering mosfets to my old motherboard last night.
And about for those registers; all the range cleared with zero.
cyring
commented
4 months ago @EUA
OR, do you sure about if correct base address is really 0x59800 for my CPU?
Brillant suggestion you have.
Yup. Have some natural gift on beta testing. :) I have busy with soldering mosfets to my old motherboard last night.
And about for those registers; all the range cleared with zero.
If all cleared then no CCD.
And TCTL only at read_tempreg_nb_zen() which reads temperature at:
./zencli smu 0x00059800Can you try, probably again, 0x00059800 ?
EDIT : I will program another method and come back with a commit for testing.
cyring
commented
4 months ago Using your previous read of:
./zencli smu 0x00059800[0x00059800] READ(smu) = 0x822b0000 (2183856128)
60 56 52 48 44 40 36 32 28 24 20 16 12 08 04 00
0000 0000 0000 0000 0000 0000 0000 0000 1000 0010 0010 1011 0000 0000 0000 0000Now extracting bits and computing temperature:
echo $(( 0x822b0000 >> 21 ))1041echo $(( ((1041*5)/40)-49 ))81So the SMU thermal register address is definitely 0x00059800
I just merged all development commits into master which you can pull (or clone again) and test for temperature.
EUA
commented
4 months ago So what could be a problem? Some kernel options are not allowing to read them? Temperature value is start to appear. But not for each core, yet...
cyring
commented
4 months ago So what could be a problem? Some kernel options are not allowing to read them? Temperature value is start to appear. But not for each core, yet...
Cam you show me screenshots ?
In contrary to CCD, TCTL has to be be a single sensor so the reading scope should be Package in "Settings" window.
EUA
commented
4 months ago I got it. This from TCL, not CCD. At HWINFO (windows), we got detailed voltage and temperature info belongs to each core. Not one temp applied to each core. So, this is misleading. For now, unfil figure to read CCD from chip,it's better to not show SMT or Core but "Package" automatically at settings for 8000 Series APUs,...
Noticed that, core 010 minimum reported as 64... It's just a sw glitch I think. otherwise if you torture CPU 1, also CPU10 reports same value.
cyring
commented
4 months ago I got it. This from TCL, not CCD. At HWINFO (windows), we got detailed voltage and temperature info belongs to each core. Not one temp applied to each core. So, this is misleading. For now, unfil figure to read CCD from chip,it's better to not show SMT or Core but "Package" automatically at settings for 8000 Series APUs,...
Sure it will be part of next commit.
Phoenix v1 & v2 will also be set the same default.
However I need Phoenix owners to help me confirm the SMU thermal register.
My understanding is that Hawk Point is a single CCD: can you show the Core Topology ?
corefreq-cli -mIf true then TCTL is shared among all Cores: like any previous Ryzen generation
Noticed that, core 010 minimum reported as 64... It's just a sw glitch I think. otherwise if you torture CPU 1, also CPU10 reports same value.
Please show me as many screenshots and/or outputs as possible because it's difficult from here to figure what's the issue is.
Also sensors screenshots of HWINFO when a single and only one CPU is stressed out.
EUA
commented
4 months ago Indeed, at APU series, there are no discrete CCD as other Ryzen 7000 CPUs. All is made from a single piece of silicon which includes the "CCD" complex. This might be a reason about why your 7000 series code not work on APU.
Also different minimum report is not really important since it will be fade away with proper CCD thermal implementation...
Here is the info:
[root@Ryzen CoreFreq]# ./build/corefreq-cli -m
CPU Pkg Apic Core/Thread Caches (w)rite-Back (i)nclusive
# ID ID CCD CCX ID/ID L1-Inst Way L1-Data Way L2 Way L3 Way
000:BSP 0 0 0 0 0 32 8 32 8 1024 8 i 16384 16w
001: 0 2 0 0 1 0 32 8 32 8 1024 8 i 16384 16w
002: 0 4 0 0 2 0 32 8 32 8 1024 8 i 16384 16w
003: 0 6 0 0 3 0 32 8 32 8 1024 8 i 16384 16w
004: 0 8 0 1 4 0 32 8 32 8 1024 8 i 16384 16w
005: 0 10 0 1 5 0 32 8 32 8 1024 8 i 16384 16w
006: 0 1 0 0 0 1 32 8 32 8 1024 8 i 16384 16w
007: 0 3 0 0 1 1 32 8 32 8 1024 8 i 16384 16w
008: 0 5 0 0 2 1 32 8 32 8 1024 8 i 16384 16w
009: 0 7 0 0 3 1 32 8 32 8 1024 8 i 16384 16w
010: 0 9 0 1 4 1 32 8 32 8 1024 8 i 16384 16w
011: 0 11 0 1 5 1 32 8 32 8 1024 8 i 16384 16w Also my HWINFO
cyring
commented
4 months ago @EUA
Last commit 3778ece916d702fe3811f387bc77b469b0552733 I'm removing Complex from the APU topology
Can you please test the change and post corefreq-cli -m
About HWINFO, I've no idea which those GFX temperature registers are ?
cyring
commented
4 months ago Hello
Actions are transferred into #424 and a Wiki page is added for Ryzen 5 8600G
EUA
commented
4 months ago [root@Ryzen CoreFreq]# ./build/corefreq-cli -m
CPU Pkg Apic Core/Thread Caches (w)rite-Back (i)nclusive
# ID ID ID ID L1-Inst Way L1-Data Way L2 Way L3 Way
000:BSP 0 0 0 32 8 32 8 1024 8 i 16384 16w
001: 0 2 1 0 32 8 32 8 1024 8 i 16384 16w
002: 0 4 2 0 32 8 32 8 1024 8 i 16384 16w
003: 0 6 3 0 32 8 32 8 1024 8 i 16384 16w
004: 0 8 4 0 32 8 32 8 1024 8 i 16384 16w
005: 0 10 5 0 32 8 32 8 1024 8 i 16384 16w
006: 0 1 0 1 32 8 32 8 1024 8 i 16384 16w
007: 0 3 1 1 32 8 32 8 1024 8 i 16384 16w
008: 0 5 2 1 32 8 32 8 1024 8 i 16384 16w
009: 0 7 3 1 32 8 32 8 1024 8 i 16384 16w
010: 0 9 4 1 32 8 32 8 1024 8 i 16384 16w
011: 0 11 5 1 32 8 32 8 1024 8 i 16384 16w
Since APU has GPU in it, CoreFreq might show the GPU clock also. Because soon gcc start to move some threads into GPU section at APU... So it counts as core too. Just brainstorming.
cyring
commented
4 months ago The main issue is solved and the remaining actions are in list to do after this release candidate. Thank you very much for your help. Feel free to close your issue.
Hi, Thanks for great program. I got Ryzen 1700 with B350 MB. I enabled deep sleep at bios etc... I tried to do everything but don't have any success.
corefreq only shows Turbo, C0 and C1 states. It shown at program that (CC6 & PC6 green) but C3/C6/C7 counters are always zero at frequency and Idle C-states view.
Why does C3/C6/C7 states not supported by CoreFreq?
PS: using cpupower monitor give this result.