Closed cyring closed 5 years ago
adatum
commented
5 years ago Changing 1C ratio isn't actually changing the frequency ratio as seen in the max ratio value and the frequency reading during a burn test:
Also, upon restoring Boost, the cpu is still stuck to a maximum of 3.7 GHz.
cyring
commented
5 years ago Don't you reach a ratio of 39 when burning one and only core ?
It may work like Intel when set for a one core ratio, you need to stress one, and only one CPU
The same with 2C, you reach the defined ratio when 2 CPU are only loaded (plus other processor limits: TDP)
You can use the integrated stress tool [F3] and choose 'Turbo Random CPU' or 'Turbo Round Robin' to burn 1C
Also try to disable CC6 and PC6
It may overclock with the 2C P-State ?
Boost restoring is a remaining task but unlike Intel, none AMD register is giving me the factory ratio values.
As current code, I can compute 1C with the max non turbo (factory 37) then add XFR but what about 2C or 3C...
cyring
commented
5 years ago In AMD specs, I'm reading the MSRC001_0061 [P-state Current Limit]
| Bits | Description |
|---|---|
|
Reserved. |
|
PstateMaxVal: P-state maximum value. Read,Error-on-write,Volatile. Reset: XXXb.Specifies the lowest-performance non-boosted P-state (highest non-boosted value) allowed. |
|
Reserved. Read-only. Reset: Fixed,0. |
|
CurPstateLimit: current P-state limit. Read,Error-on-write,Volatile. Reset: XXXb.Specifies the highest-performance P-state (lowest value) allowed. |
These could be reliable values to restore ratio when restoring Boost.
Can you please rdmsr 0xC0010061 before then after changing ratio. Also when restoring boost ?
adatum
commented
5 years ago AMD's boost is different than Intel's and kind of complicated with PB2, XFR2, and PBO algorithmically managing multi-core boosting depending on various safety limits. The trouble is that those technologies are named differently in the BIOS, depending on the vendor. Some info about the boosting here, here, here, and here.
Normally the all-core frequency I see is at least 3.8GHz up to 4.1GHz depending on the type of load.
But I don't think the ratio actually changed because I tried higher (39), and also lower (34) ratios, but the stress test always resulted in the same 3.7GHz all-core frequency. I also tried with CC6 and PC6 disabled.
Also, my understanding is that when manually overclocking, defined by changing the ratio from the stock 37, it is an all-core overclock.
Without changing ratio rdmsr 0xC0010061 reads 20. The trouble with testing the ratio right now is that the only way I have found to get the normal boosting back is to reboot.
cyring
commented
5 years ago Sorry for the reboot inconvenience. I hope we could find a way to restore values online. Also about MSR 0xC0010061 we have already worked on it https://github.com/cyring/CoreFreq/issues/54#issuecomment-392280424 . Those registers don't supply ratios but just P-States. I could compute the core coefficient from them but how to be sure they have not been altered since reboot.
As shown in some BIOS screens, perhaps the OC works when applied to P-State P0
Could you replace this function with the following code: https://github.com/cyring/CoreFreq/blob/677adf07ac05ab310ccf5a945cd36f3fac00913f/corefreqk.c#L3132
long TurboClock_AMD_Zen(CLOCK_ARG *pClockMod)
{
long rc = 0;
if (Proc->Registration.Experimental)
{
HWCR HwCfgRegister = {.value = 0};
/* Make sure the Core Performance Boost is disabled. */
RDMSR(HwCfgRegister, MSR_K7_HWCR);
if (HwCfgRegister.Family_17h.CpbDis && (pClockMod != NULL)) {
unsigned long long PstateAddr = MSR_AMD_PSTATE_DEF_BASE;
PSTATEDEF PstateDef = {.value = 0};
/* switch (pClockMod->Ratio) {
case 1 ... 7:
PstateAddr += pClockMod->Ratio; */
RDMSR(PstateDef, PstateAddr);
/* Apply if and only if the P-State is enabled */
if (PstateDef.Family_17h.PstateEn) {
/* unsigned int index = BOOST(SIZE) - pClockMod->Ratio;*/
unsigned int index = BOOST(MAX);
/* Compute the P-State Frequency ID from the ratio */
unsigned int FID = 0, COF = 0;
FID = AMD_Zen_CoreFID( Proc->Boost[index]
+ pClockMod->Offset,
PstateDef.Family_17h.CpuDfsId);
/* Write then Read the P-State MSR */
PstateDef.Family_17h.CpuFid = FID;
WRMSR(PstateDef, PstateAddr);
RDMSR(PstateDef, PstateAddr);
/* Re-compute the Core coefficient */
COF = AMD_Zen_CoreCOF( PstateDef.Family_17h.CpuFid,
PstateDef.Family_17h.CpuDfsId);
/* Update the Boost ratio with COF */
Proc->Boost[index] = COF;
rc = 2;
}
/* break;
} */
}
}
return(rc);
}This code will add any selected offset (last column) to the Max Frequency (aka P0 State)
For example, you select +2 in the [Turbo Clock 1C] window then the Max Frequency should be OCed to 37 + 2 = 39
adatum
commented
5 years ago rdmsr 0xC0010061 reads 20 before and after changing ratio, and with Boost enabled/disabled. Note that when we tested MSR readings before, I had the default values in BIOS for Core Performance Boost (CPB) and Performance Boost Override/Overdrive (PBO), both at Auto/defaults. Now they are at Enabled. I'm not sure if CPB Enabled is the same as Auto (it might be, but Asus doesn't make it clear what the defaults are), but enabling PBO definitely made a difference in the all-core frequency under load.
I tried the modified function code above. The +/- increments work for the ratio, but the MHz displayed next to them in the overclocking window don't seem to match what is applied. eg. after selecting -2 to result in 35, selecting 4000 MHz doesn't result in that value for max frequency, but rather applies the ratio increment (or decrement) specified in that row.
A possible reason is that somehow the base clock was being changed! It's not clear to me if it's a reporting issue or if the base clock was really modified. However I have a hard time believing values in the screenshot, since OCers usually barely manage 102-104 MHz before getting an unstable system. But that is with synchronized base clocks. This motherboard also has the option of varying the system and cpu bus clocks independently (at the cost of latency). I noticed the base clock changes only after testing some ratios and it worried me so I rebooted. Also notice the discrepancy between the base clock value in the Processor window and CoreFreq's header.
Also, the cores were uneven in the frequency they reached with an underclock to 36. I found that odd since throttling should not be an issue at those low frequencies and temperatures. Notice that the base clock is reportedly changed here too (the screenshot below was taken before the one above).
cyring
commented
5 years ago A new version is pushed which splits the logic between the Min-Max ratios and the Turbo ratios. With Zen, the Max Frequency ratio is the one to test.
The Base Clock is estimated every sec and updated in the header but not in the Processor window.
For the test, I recommend to start the driver with the argument AutoClock=0. You will get 100MHz
adatum
commented
5 years ago For the test, I recommend to start the driver with the argument AutoClock=0. You will get 100MHz
- Increase the ratio by one unit then apply load to check the result
- Next, decrease by one unit to check if frequency is back to nominal.
This worked with changing Max Frequency ratio, but increasing +1 (38) resulted in a 200 MHz jump (3900 MHz) when load testing single CPU in round robin. Decreasing by -1 back to 37 also worked and load testing saw 3700 MHz.
Also, the Atomic Burn test, after moving the ratio +1 and also -1, made CoreFreq unresponsive for a while and practically froze the entire computer (not normal). This testing feels rather risky, much more so than what we've previously done.
After testing and re-enabling CBP, the actual max frequency is still capped at 3700 MHz.
cyring
commented
5 years ago So it went from 3.7 to 4.0 GHz despite you have selected 3.8 GHz. I suspect a mathematical rounding issue. Zen can do decimal frequencies (.25 ; .5 ; .75)
It might also be necessary to delay after modifying the FID in the P-State register. But I don't read such thing in specs. However, I found a bit to set the TSC to the new P-State frequency. This may solve the BCLK issue you have noticed.
Is it also unresponsive when testing with an external stress tool ?
adatum
commented
5 years ago Is it also unresponsive when testing with an external stress tool ?
Not sure why, but I could not reproduce the unresponsiveness when I tried the steps again.
Here's a screenshot of the 3900 MHz frequency with max frequency ratio set to 38:
A thought about the inability to go back to boosting after OC: setting a ratio other than 37 results in a manual OC and from my understanding automatically disables certain features. I've always wondered whether it's possible to set a manual "OC" to 37, and if so what's the difference between that and keeping a default non-OC 37 ratio. Maybe there is a detail here that is the cause of losing boosting with after changing ratios with CoreFreq?
cyring
commented
5 years ago Hello,
Could you rdmsr on CPU #0 and #7 the following registers in those situations:
| When | PStateDef0xc0010064 |
HWCR0xc0010015 |
Unknown PState0xc0010293 |
|---|---|---|---|
| BIOS Boost Enabled [nominal] | |||
| BIOS Overclock @ 3800 MHz | |||
| BIOS Overclock @ 3900 MHz |
Please report results in hexadecimal.
cyring
commented
5 years ago I have brought code changes to overclock per Core. Can you please try the last version ?
cyring
commented
5 years ago ... and also print corefreq-cli -s
adatum
commented
5 years ago By Boost you mean CPB, yes? FYI, PBO is also enabled.
So far CPU #0 and #7 give the same rdmsr readings.
| When | PStateDef 0xc0010064 |
HWCR 0xc0010015 |
Unknown PState 0xc0010293 |
|---|---|---|---|
| BIOS Boost Enabled [nominal] | 80000000494d8894 | 9000011 | Varies: 8550ae, 97cc80, 9ccc84, 978c80, 974c80, 97cc84, 5d0880, 8510ae, 980c80, 9d0c80, 83cc80, 840c80, 8390ae, 608ae, 580880, 84cc80, 448ae, etc |
| BIOS Overclock @ 3800 MHz | 80000000494ac898 | 4b000011 | Varies: 4b0c87, 8b0e87, 8b0e98, b0898, etc |
| BIOS Overclock @ 3900 MHz | 80000000494ac89c | 4b000011 | Varies: 4b0c87, b089c, 8b0e9c, 8b0e87, 8b109c, etc |
corefreq-cli -s with BIOS CPB Enabled:
$ ./corefreq-cli -s
Processor [AMD Ryzen 7 2700X Eight-Core Processor ]
|- Architecture [Zen+ Pinnacle Ridge]
|- Vendor ID [AuthenticAMD]
|- Signature [ 8F_08]
|- Stepping [ 2]
|- Microcode [ 0]
|- Online CPU [ 16/16]
|- Base Clock [100.00]
|- Frequency (Mhz) Ratio
Min 400.00 [ 4 ]
Max 3700.00 < 37 >
|- Factory [100.00]
3700 [ 37 ]
|- Turbo Boost [UNLOCK]
1C 4400.00 < 44 >
2C 3200.00 < 32 >
3C 2200.00 < 22 >
|- Uncore [ LOCK]
ISA Extensions:
|- 3DNow!/Ext [N,N] ADX [Y] AES [Y] AVX/AVX2 [Y/Y]
|- AVX-512 [N] BMI1/BMI2 [Y/Y] CLFSH [Y] CMOV [Y]
|- CMPXCH8 [Y] CMPXCH16 [Y] F16C [Y] FPU [Y]
|- FXSR [Y] LAHF/SAHF [Y] MMX/Ext [Y/Y] MONITOR [Y]
|- MOVBE [Y] MPX [N] PCLMULDQ [Y] POPCNT [Y]
|- RDRAND [Y] RDSEED [Y] RDTSCP [Y] SEP [Y]
|- SGX [N] SSE [Y] SSE2 [Y] SSE3 [Y]
|- SSSE3 [Y] SSE4.1/4A [Y/Y] SSE4.2 [Y] SYSCALL [Y]
Features:
|- 1 GB Pages Support 1GB-PAGES [Present]
|- 100 MHz multiplier Control 100MHzSteps [Missing]
|- Advanced Configuration & Power Interface ACPI [Present]
|- Advanced Programmable Interrupt Controller APIC [Present]
|- Core Multi-Processing CMP Legacy [Present]
|- L1 Data Cache Context ID CNXT-ID [Missing]
|- Direct Cache Access DCA [Missing]
|- Debugging Extension DE [Present]
|- Debug Store & Precise Event Based Sampling DS, PEBS [Missing]
|- CPL Qualified Debug Store DS-CPL [Missing]
|- 64-Bit Debug Store DTES64 [Missing]
|- Fast-String Operation Fast-Strings [Missing]
|- Fused Multiply Add FMA|FMA4 [Present]
|- Hardware Lock Elision HLE [Missing]
|- Long Mode 64 bits IA64|LM [Present]
|- LightWeight Profiling LWP [Missing]
|- Machine-Check Architecture MCA [Present]
|- Model Specific Registers MSR [Present]
|- Memory Type Range Registers MTRR [Present]
|- No-Execute Page Protection NX [Present]
|- OS-Enabled Ext. State Management OSXSAVE [Present]
|- Physical Address Extension PAE [Present]
|- Page Attribute Table PAT [Present]
|- Pending Break Enable PBE [Missing]
|- Process Context Identifiers PCID [Missing]
|- Perfmon and Debug Capability PDCM [Missing]
|- Page Global Enable PGE [Present]
|- Page Size Extension PSE [Present]
|- 36-bit Page Size Extension PSE36 [Present]
|- Processor Serial Number PSN [Missing]
|- Restricted Transactional Memory RTM [Missing]
|- Safer Mode Extensions SMX [Missing]
|- Self-Snoop SS [Missing]
|- Time Stamp Counter TSC [Invariant]
|- Time Stamp Counter Deadline TSC-DEADLINE [Missing]
|- Virtual Mode Extension VME [Present]
|- Virtual Machine Extensions VMX [Missing]
|- Extended xAPIC Support x2APIC [Missing]
|- XSAVE/XSTOR States XSAVE [Present]
|- xTPR Update Control xTPR [Missing]
Technologies:
|- System Management Mode SMM-Lock [ ON]
|- Simultaneous Multithreading SMT [ ON]
|- PowerNow! CnQ [OFF]
|- Core Performance Boost CPB < ON>
|- Virtualization SVM [ ON]
|- I/O MMU AMD-V [OFF]
|- Hypervisor [OFF]
Performance Monitoring:
|- Version PM [ 0]
|- Counters: General Fixed
| 6 x 64 bits 3 x 64 bits
|- Enhanced Halt State C1E <OFF>
|- Core C6 State CC6 < ON>
|- Package C6 State PC6 < ON>
|- Frequency ID control FID [OFF]
|- Voltage ID control VID [OFF]
|- P-State Hardware Coordination Feedback MPERF/APERF [ ON]
|- Hardware-Controlled Performance States HWP [ ON]
|- Hardware Duty Cycling HDC [OFF]
|- Package C-State
|- Configuration Control CONFIG [ LOCK]
|- Lowest C-State LIMIT [ 0]
|- I/O MWAIT Redirection IOMWAIT [DISABLE]
|- Max C-State Inclusion RANGE [ 0]
|- MWAIT States: C0 C1 C2 C3 C4
| 1 1 0 0 0
|- Core Cycles [Present]
|- Instructions Retired [Present]
|- Reference Cycles [Present]
|- Last Level Cache References [Missing]
|- Last Level Cache Misses [Missing]
|- Branch Instructions Retired [Missing]
|- Branch Mispredicts Retired [Missing]
Power & Thermal Monitoring:
|- Clock Modulation ODCM <Disable>
|- DutyCycle < 0.00%>
|- Power Management PWR MGMT [ LOCK]
|- Energy Policy Bias Hint [ 0]
|- Junction Temperature TjMax [ 49: 10]
|- Digital Thermal Sensor DTS [Present]
|- Power Limit Notification PLN [Missing]
|- Package Thermal Management PTM [Missing]
|- Thermal Monitor 1 TM1|TTP [Present]
|- Thermal Monitor 2 TM2|HTC [Present]
|- Units
|- Power watt [ 0.015625000]
|- Energy joule [ 0.000001907]
|- Window second [ 0.000976562]corefreq-cli -s with BIOS Overclock @ 3800 MHz:
$ ./corefreq-cli -s
Processor [AMD Ryzen 7 2700X Eight-Core Processor ]
|- Architecture [Zen+ Pinnacle Ridge]
|- Vendor ID [AuthenticAMD]
|- Signature [ 8F_08]
|- Stepping [ 2]
|- Microcode [ 0]
|- Online CPU [ 16/16]
|- Base Clock [100.00]
|- Frequency (Mhz) Ratio
Min 400.00 [ 4 ]
Max 3800.00 < 38 >
|- Factory [100.00]
3800 [ 38 ]
|- Turbo Boost [UNLOCK]
1C 3800.00 < 38 >
2C 2200.00 < 22 >
3C 2200.00 < 22 >
|- Uncore [ LOCK]
ISA Extensions:
|- 3DNow!/Ext [N,N] ADX [Y] AES [Y] AVX/AVX2 [Y/Y]
|- AVX-512 [N] BMI1/BMI2 [Y/Y] CLFSH [Y] CMOV [Y]
|- CMPXCH8 [Y] CMPXCH16 [Y] F16C [Y] FPU [Y]
|- FXSR [Y] LAHF/SAHF [Y] MMX/Ext [Y/Y] MONITOR [Y]
|- MOVBE [Y] MPX [N] PCLMULDQ [Y] POPCNT [Y]
|- RDRAND [Y] RDSEED [Y] RDTSCP [Y] SEP [Y]
|- SGX [N] SSE [Y] SSE2 [Y] SSE3 [Y]
|- SSSE3 [Y] SSE4.1/4A [Y/Y] SSE4.2 [Y] SYSCALL [Y]
Features:
|- 1 GB Pages Support 1GB-PAGES [Present]
|- 100 MHz multiplier Control 100MHzSteps [Missing]
|- Advanced Configuration & Power Interface ACPI [Present]
|- Advanced Programmable Interrupt Controller APIC [Present]
|- Core Multi-Processing CMP Legacy [Present]
|- L1 Data Cache Context ID CNXT-ID [Missing]
|- Direct Cache Access DCA [Missing]
|- Debugging Extension DE [Present]
|- Debug Store & Precise Event Based Sampling DS, PEBS [Missing]
|- CPL Qualified Debug Store DS-CPL [Missing]
|- 64-Bit Debug Store DTES64 [Missing]
|- Fast-String Operation Fast-Strings [Missing]
|- Fused Multiply Add FMA|FMA4 [Present]
|- Hardware Lock Elision HLE [Missing]
|- Long Mode 64 bits IA64|LM [Present]
|- LightWeight Profiling LWP [Missing]
|- Machine-Check Architecture MCA [Present]
|- Model Specific Registers MSR [Present]
|- Memory Type Range Registers MTRR [Present]
|- No-Execute Page Protection NX [Present]
|- OS-Enabled Ext. State Management OSXSAVE [Present]
|- Physical Address Extension PAE [Present]
|- Page Attribute Table PAT [Present]
|- Pending Break Enable PBE [Missing]
|- Process Context Identifiers PCID [Missing]
|- Perfmon and Debug Capability PDCM [Missing]
|- Page Global Enable PGE [Present]
|- Page Size Extension PSE [Present]
|- 36-bit Page Size Extension PSE36 [Present]
|- Processor Serial Number PSN [Missing]
|- Restricted Transactional Memory RTM [Missing]
|- Safer Mode Extensions SMX [Missing]
|- Self-Snoop SS [Missing]
|- Time Stamp Counter TSC [Invariant]
|- Time Stamp Counter Deadline TSC-DEADLINE [Missing]
|- Virtual Mode Extension VME [Present]
|- Virtual Machine Extensions VMX [Missing]
|- Extended xAPIC Support x2APIC [Missing]
|- XSAVE/XSTOR States XSAVE [Present]
|- xTPR Update Control xTPR [Missing]
Technologies:
|- System Management Mode SMM-Lock [ ON]
|- Simultaneous Multithreading SMT [ ON]
|- PowerNow! CnQ [OFF]
|- Core Performance Boost CPB <OFF>
|- Virtualization SVM [ ON]
|- I/O MMU AMD-V [OFF]
|- Hypervisor [OFF]
Performance Monitoring:
|- Version PM [ 0]
|- Counters: General Fixed
| 6 x 64 bits 3 x 64 bits
|- Enhanced Halt State C1E <OFF>
|- Core C6 State CC6 <OFF>
|- Package C6 State PC6 < ON>
|- Frequency ID control FID [ ON]
|- Voltage ID control VID [ ON]
|- P-State Hardware Coordination Feedback MPERF/APERF [ ON]
|- Hardware-Controlled Performance States HWP [ ON]
|- Hardware Duty Cycling HDC [OFF]
|- Package C-State
|- Configuration Control CONFIG [ LOCK]
|- Lowest C-State LIMIT [ 0]
|- I/O MWAIT Redirection IOMWAIT [DISABLE]
|- Max C-State Inclusion RANGE [ 0]
|- MWAIT States: C0 C1 C2 C3 C4
| 1 1 0 0 0
|- Core Cycles [Present]
|- Instructions Retired [Present]
|- Reference Cycles [Present]
|- Last Level Cache References [Missing]
|- Last Level Cache Misses [Missing]
|- Branch Instructions Retired [Missing]
|- Branch Mispredicts Retired [Missing]
Power & Thermal Monitoring:
|- Clock Modulation ODCM <Disable>
|- DutyCycle < 0.00%>
|- Power Management PWR MGMT [ LOCK]
|- Energy Policy Bias Hint [ 0]
|- Junction Temperature TjMax [ 49: 10]
|- Digital Thermal Sensor DTS [Present]
|- Power Limit Notification PLN [Missing]
|- Package Thermal Management PTM [Missing]
|- Thermal Monitor 1 TM1|TTP [Present]
|- Thermal Monitor 2 TM2|HTC [Present]
|- Units
|- Power watt [ 0.015625000]
|- Energy joule [ 0.000001907]
|- Window second [ 0.000976562]corefreq-cli -s with BIOS Overclock @ 3900 MHz:
$ ./corefreq-cli -s
Processor [AMD Ryzen 7 2700X Eight-Core Processor ]
|- Architecture [Zen+ Pinnacle Ridge]
|- Vendor ID [AuthenticAMD]
|- Signature [ 8F_08]
|- Stepping [ 2]
|- Microcode [ 0]
|- Online CPU [ 16/16]
|- Base Clock [100.00]
|- Frequency (Mhz) Ratio
Min 400.00 [ 4 ]
Max 3900.00 < 39 >
|- Factory [100.00]
3900 [ 39 ]
|- Turbo Boost [UNLOCK]
1C 3900.00 < 39 >
2C 2200.00 < 22 >
3C 2200.00 < 22 >
|- Uncore [ LOCK]
ISA Extensions:
|- 3DNow!/Ext [N,N] ADX [Y] AES [Y] AVX/AVX2 [Y/Y]
|- AVX-512 [N] BMI1/BMI2 [Y/Y] CLFSH [Y] CMOV [Y]
|- CMPXCH8 [Y] CMPXCH16 [Y] F16C [Y] FPU [Y]
|- FXSR [Y] LAHF/SAHF [Y] MMX/Ext [Y/Y] MONITOR [Y]
|- MOVBE [Y] MPX [N] PCLMULDQ [Y] POPCNT [Y]
|- RDRAND [Y] RDSEED [Y] RDTSCP [Y] SEP [Y]
|- SGX [N] SSE [Y] SSE2 [Y] SSE3 [Y]
|- SSSE3 [Y] SSE4.1/4A [Y/Y] SSE4.2 [Y] SYSCALL [Y]
Features:
|- 1 GB Pages Support 1GB-PAGES [Present]
|- 100 MHz multiplier Control 100MHzSteps [Missing]
|- Advanced Configuration & Power Interface ACPI [Present]
|- Advanced Programmable Interrupt Controller APIC [Present]
|- Core Multi-Processing CMP Legacy [Present]
|- L1 Data Cache Context ID CNXT-ID [Missing]
|- Direct Cache Access DCA [Missing]
|- Debugging Extension DE [Present]
|- Debug Store & Precise Event Based Sampling DS, PEBS [Missing]
|- CPL Qualified Debug Store DS-CPL [Missing]
|- 64-Bit Debug Store DTES64 [Missing]
|- Fast-String Operation Fast-Strings [Missing]
|- Fused Multiply Add FMA|FMA4 [Present]
|- Hardware Lock Elision HLE [Missing]
|- Long Mode 64 bits IA64|LM [Present]
|- LightWeight Profiling LWP [Missing]
|- Machine-Check Architecture MCA [Present]
|- Model Specific Registers MSR [Present]
|- Memory Type Range Registers MTRR [Present]
|- No-Execute Page Protection NX [Present]
|- OS-Enabled Ext. State Management OSXSAVE [Present]
|- Physical Address Extension PAE [Present]
|- Page Attribute Table PAT [Present]
|- Pending Break Enable PBE [Missing]
|- Process Context Identifiers PCID [Missing]
|- Perfmon and Debug Capability PDCM [Missing]
|- Page Global Enable PGE [Present]
|- Page Size Extension PSE [Present]
|- 36-bit Page Size Extension PSE36 [Present]
|- Processor Serial Number PSN [Missing]
|- Restricted Transactional Memory RTM [Missing]
|- Safer Mode Extensions SMX [Missing]
|- Self-Snoop SS [Missing]
|- Time Stamp Counter TSC [Invariant]
|- Time Stamp Counter Deadline TSC-DEADLINE [Missing]
|- Virtual Mode Extension VME [Present]
|- Virtual Machine Extensions VMX [Missing]
|- Extended xAPIC Support x2APIC [Missing]
|- XSAVE/XSTOR States XSAVE [Present]
|- xTPR Update Control xTPR [Missing]
Technologies:
|- System Management Mode SMM-Lock [ ON]
|- Simultaneous Multithreading SMT [ ON]
|- PowerNow! CnQ [OFF]
|- Core Performance Boost CPB <OFF>
|- Virtualization SVM [ ON]
|- I/O MMU AMD-V [OFF]
|- Hypervisor [OFF]
Performance Monitoring:
|- Version PM [ 0]
|- Counters: General Fixed
| 6 x 64 bits 3 x 64 bits
|- Enhanced Halt State C1E <OFF>
|- Core C6 State CC6 <OFF>
|- Package C6 State PC6 < ON>
|- Frequency ID control FID [ ON]
|- Voltage ID control VID [ ON]
|- P-State Hardware Coordination Feedback MPERF/APERF [ ON]
|- Hardware-Controlled Performance States HWP [ ON]
|- Hardware Duty Cycling HDC [OFF]
|- Package C-State
|- Configuration Control CONFIG [ LOCK]
|- Lowest C-State LIMIT [ 0]
|- I/O MWAIT Redirection IOMWAIT [DISABLE]
|- Max C-State Inclusion RANGE [ 0]
|- MWAIT States: C0 C1 C2 C3 C4
| 1 1 0 0 0
|- Core Cycles [Present]
|- Instructions Retired [Present]
|- Reference Cycles [Present]
|- Last Level Cache References [Missing]
|- Last Level Cache Misses [Missing]
|- Branch Instructions Retired [Missing]
|- Branch Mispredicts Retired [Missing]
Power & Thermal Monitoring:
|- Clock Modulation ODCM <Disable>
|- DutyCycle < 0.00%>
|- Power Management PWR MGMT [ LOCK]
|- Energy Policy Bias Hint [ 0]
|- Junction Temperature TjMax [ 49: 10]
|- Digital Thermal Sensor DTS [Present]
|- Power Limit Notification PLN [Missing]
|- Package Thermal Management PTM [Missing]
|- Thermal Monitor 1 TM1|TTP [Present]
|- Thermal Monitor 2 TM2|HTC [Present]
|- Units
|- Power watt [ 0.015625000]
|- Energy joule [ 0.000001907]
|- Window second [ 0.000976562]Yes I meant CPB. Meanwhile I have pushed code which hopefully can overclock the Ryzen. You may have to clone again What's new is that I now modify the frequency on all Zen cores (thread scope) whereas Intel processors use common registers (package scope)
adatum
commented
5 years ago All done with the latest code.
cyring
commented
5 years ago Thanks. I will analyze those bits... Can you try now to overclock from CoreFreq UI b/c the algorithm has changed.
adatum
commented
5 years ago Changing the Max Frequency ratio results in the corresponding single- and multi-core frequencies when stress tested.
There is still the issue of being unable to restore CPB through the CoreFreq UI after disabling it for overclocking.
cyring
commented
5 years ago Beside the CpbDis and IRPerfEn flags, the HWCR register values do not show major differences between CPB and overclocking in BIOS.
I don't have a factory ratio to restore CPB with. When overclocking is activated in BIOS, the nominal ratio is overrided (the initial ratio stored in P0 P-State can not be retrieved by any known registers). You will have to do things manually and write down the max frequency, like bellow.
A new version is available for testing.
Boot with BIOS CPB = ON. From CoreFreq :
In the Processor view: write down the max frequency ratio (which should be 37)
In the Technology view: disable Turbo
In the Processor view: select a new max frequency ratio
Stress and check this new overclock frequency
In the Processor view: restore the nominal max frequency ratio (select 37)
In the Technology view: enable Turbo
Stress and check if Boost and XFR are in effect.
Can you also overclock the 1C, 2C, 3C ratios and see what's going on.
(please provide screenshots, better video screen, this helps me to chase bugs)
adatum
commented
5 years ago It works fine until step 7-8. When restoring CPB, 1C, 2C don't change back to what they were before. Manually trying to restore them to the original values doesn't seem to work. The max frequency is 3700 MHz from step 8 onward.
Pre-OC:
OC:
Post-OC:
Got 1C to 44 but then 2C dropped to 22. Changing 3C to 20 made it vanish. The Turbo ratios are behaving strangely.
cyring
commented
5 years ago Nice progress😎
It's hard to tell the magic inside P-States without further specifications from manufacturer
Probably, CPB has to be disabled prior changing one of the Turbo ratio (1C).
How is the BCLK estimation behaving with this version ?
Can you test the max frequency overclocking without the driver argument AutoClock
cyring
commented
5 years ago Btw I don't alter the voltage VID. This requires to work directly with the hardware and to observe any slight change.
Thus overclocking is limited to the default P-State voltage. In your case the VID provided during boot time and BIOS settings.
adatum
commented
5 years ago BCLK was reading 99.81 MHz without the AutoClock argument. While changing ratios for a bit, I did not notice the BCLK change much if at all.
Disabling/re-enabling CPB does seem to make a difference with the Turbo ratios. eg. when 3C disappears, disabling and re-enabling CPB brings it back.
But changing the Turbo ratios are like a game of whack-a-mole. Changing one ratio sometimes changes other ratios. And re-enabling CPB sometimes results in weird setups like having 2C with a higher ratio than 1C.
Also my system has totally locked up a couple of times while changing ratios.
cyring
commented
5 years ago Thanks for your reply. Restoring the CPB will be a long road. I wonder how the BIOS is managing that; beside rebooting to safe values.
There's an "enablement" bit in each of the 8 P-State registers, from P0 to P7
My algorithm don't take into account a disabled P-State
Consequently a disabled P-State won't show into the frequency view (as 1C, 2C,... 7C)
When starting up corefreqk.ko finds 4 enabled P-States in your system which translates into :
Max freq. = P0
1C = P1
2C = P2
3C = P3
Min freq. being a hard coded value, based on datasheet.
Remark: Boost and XFR are added to 1C if and only if CPB is ON else 1C = P1
Like the VID, the enablement bit is left unchanged and I don't know yet why the 3C had vanished. If it is a bug or a processor rule.
cyring
commented
5 years ago Can you please replace the following function with the code below and try OC and CPB restore. https://github.com/cyring/CoreFreq/blob/ff031e1f3b9d0fdfd0608747f44f1561b78eb7be/corefreqk.c#L3088
void Compute_AMD_Zen_Boost(void)
{
PROCESSOR_SPECIFIC *pSpecific = NULL;
unsigned int COF = 0, pstate, sort[8] = { /* P[0..7]-States */
BOOST(MAX), BOOST(1C), BOOST(2C), BOOST(3C),
BOOST(4C) , BOOST(5C), BOOST(6C), BOOST(7C)
};
HWCR HwCfgRegister = {.value = 0};
PSTATEDEF PstateDef = {.value = 0};
for (pstate = BOOST(MIN); pstate < BOOST(SIZE); pstate++)
Proc->Boost[pstate] = 0;
/*Core & L3 frequencies < 400MHz are not supported by the architecture*/
Proc->Boost[BOOST(MIN)] = 4;
/* Loop over all frequency ids. */
for (pstate = 0; pstate <= 7; pstate++) {
RDMSR(PstateDef, (MSR_AMD_PSTATE_DEF_BASE + pstate));
/* Handle only valid P-States. */
if (PstateDef.Family_17h.PstateEn) {
COF = AMD_Zen_CoreCOF( PstateDef.Family_17h.CpuFid,
PstateDef.Family_17h.CpuDfsId);
Proc->Boost[sort[pstate]] = COF;
}
}
Proc->Features.SpecTurboRatio = pstate;
/* If CPB is enabled then add Boost + XFR to the P0 ratio. */
RDMSR(HwCfgRegister, MSR_K7_HWCR);
if (!HwCfgRegister.Family_17h.CpbDis)
{
Proc->Boost[BOOST(8C)] = Proc->Boost[BOOST(MAX)];
Proc->Boost[BOOST(9C)] = Proc->Boost[BOOST(MAX)];
if ((pSpecific = LookupProcessor()) != NULL) {
/* Save thermal parameters to compute per Core temperature */
Arch[Proc->ArchID].Specific[0].Param = pSpecific->Param;
Proc->Boost[BOOST(8C)] += pSpecific->Boost[0];
Proc->Boost[BOOST(9C)] += pSpecific->Boost[0];
Proc->Boost[BOOST(9C)] += pSpecific->Boost[1]; /* XFR */
OverrideCodeNameString(pSpecific);
OverrideUnlockCapability(pSpecific);
} else {
Arch[Proc->ArchID].Specific[0].Param.Target = 0;
}
Proc->Features.SpecTurboRatio += 2;
}
}With the above code, max load frequency is not stuck at 3700 MHz after disabling/re-enabling CPB, but I think it's because there's something strange going on with BCLK again.
Also, I'm not sure I understand what you are trying to do, but I don't think AMD intends boost and XFR as fixed ratio increases.
CPB off, OC=38, AutoClock default (note 108.89 MHz which doesn't make sense):
CPB on, no OC (=37), AutoClock default:
AutoClock off (99.81 MHz):
cyring
commented
5 years ago Hello,
AMD intends boost and XFR as fixed ratio increases
Intel specifies MSR registers to query most Processor ratios [Min, Max, Turbo, Activation, Uncore, ...]; with AMD I'm just getting a few and have to refer to market values. Same misery we had with temperature offset.
About BCLK, I could have a TSC delta computing bug here: https://github.com/cyring/CoreFreq/blob/ff031e1f3b9d0fdfd0608747f44f1561b78eb7be/corefreqk.c#L7016
Could you replace with this code and check BLCK during OC and CPB
static enum hrtimer_restart Cycle_AMD_Family_17h(struct hrtimer *pTimer)
{
PSTATESTAT PstateStat;
PSTATEDEF PstateDef;
CORE *Core;
unsigned int pstate;
unsigned int cpu;
cpu = smp_processor_id();
Core = (CORE *) KPublic->Core[cpu];
Mark_OVH(Core);
if (BITVAL(KPrivate->Join[cpu]->TSM, MUSTFWD) == 1) {
hrtimer_forward(pTimer,
hrtimer_cb_get_time(pTimer),
RearmTheTimer);
SMT_Counters_AMD_Family_17h(Core, 1);
/*ToDo: Compute Core Performance Boost */
if (Core->Bind == Proc->Service.Core) {
PKG_Counters_Generic(Core, 1);
Core_AMD_Family_17h_Temp(Core);
PWR_ACCU_AMD_Family_17h(Proc, 1);
Delta_PTSC(Proc);
Delta_PWR_ACCU(Proc, PKG);
Delta_PWR_ACCU(Proc, CORES);
Save_PWR_ACCU(Proc, PKG);
Save_PWR_ACCU(Proc, CORES);
if (AutoClock & 0b10)
Pkg_OVH(Proc, Core);
Save_PTSC(Proc);
Sys_Tick(Proc);
}
/* Read the current P-State number. */
RDMSR(PstateStat, MSR_AMD_PERF_STATUS);
/* Offset the P-State base register. */
pstate = MSR_AMD_PSTATE_DEF_BASE + PstateStat.Current;
/* Read the voltage ID at the offset */
RDMSR(PstateDef, pstate);
Core->PowerThermal.VID = PstateDef.Family_17h.CpuVid;
Delta_INST(Core);
Delta_C0(Core);
Delta_TSC(Core);
Delta_C1(Core);
Save_INST(Core);
Save_C0(Core);
Save_C1(Core);
if (AutoClock & 0b10) {
Core_OVH(Core);
REL_BCLK(Core->Clock,
Proc->Boost[BOOST(MAX)],
Core->Delta.TSC,
Proc->SleepInterval);
}
Save_TSC(Core);
BITSET(LOCKLESS, Core->Sync.V, 63);
return(HRTIMER_RESTART);
} else
return(HRTIMER_NORESTART);
}Intel specifies MSR registers to query most Processor ratios [Min, Max, Turbo, Activation, Uncore, ...]; with AMD I'm just getting a few and have to refer to market values. Same misery we had with temperature offset.
The explanations in the articles I linked to before regarding AMD's various boosting technologies indicate that they are handled dynamically by the CPU. There was an AMD marketing slide that even mentioned neural network models built into the CPU for making such decisions.
So I speculate that assigning fixed ratios will never restore the CPB behavior. I would think the CPU needs to be "informed" somehow when there is no manual OC so it can take over those functions again.
It has never been clear to me how the distinction is made: changing the multiplier from 37 means manual OC mode; but if setting it back to 37, how is a distinction made between a manual "OC" at 37, versus removing the manual OC and restoring default behavior?
One strange observation since my last testing (I haven't rebooted since): my system clock time is wrong. A few hours ago I noticed it was 35 minutes ahead, and now it has decayed to only 26 minutes ahead. I wonder if this has anything to do with possibly changing BCLK or its reading.
I tried the code above, but immediately upon starting CoreFreq the BCLK is still shown as ~108 MHz with AutoClock ON (in settings) or ~99.81 MHz with AutoClock OFF. Note that I have not rebooted the system yet since the last testing.
cyring
commented
5 years ago AMD Ryzen Master Over-clocking User’s Guide Pub. # 55931 Rev. 1.0 March 2, 2017:
The following changes take effect when the values are re-programmed and the processor enters Overclocking Mode: All enabled CPU cores operate at the newly user-programmed voltage and P0 frequency value. Adjustment of the CPU clock is in 25MHz steps.
cyring
commented
5 years ago However the Turbo bit is here: https://github.com/cyring/CoreFreq/blob/ff031e1f3b9d0fdfd0608747f44f1561b78eb7be/amdmsr.h#L140 I just reprogram the 25th bit of the msr register HWCR on all Cores to disable (value 1) or enable (0) the CPB technology, and the BOOST tag gets green or not accordingly in the UI
cyring
commented
5 years ago About BCLK it can only be a reading issue b/c I haven't found a mean to alter its frequency. Or it's an internal rule of the processor in reaction to incomplete OC settings
However I still believe the following bit has to do with a stable TSC (and by the way, your system clock) :
https://github.com/cyring/CoreFreq/blob/ff031e1f3b9d0fdfd0608747f44f1561b78eb7be/amdmsr.h#L137
That's why I asked above to collect the HWCR values when triggering OC and CPB in BIOS.
Unfortunately the LockTscToCurrP0 bit seems not to be impacted by OC
cyring
commented
5 years ago In the function Query_AMD_Zen
https://github.com/cyring/CoreFreq/blob/ff031e1f3b9d0fdfd0608747f44f1561b78eb7be/corefreqk.c#L3366
Can you replace these instructions:
case COREFREQ_TOGGLE_OFF:
case COREFREQ_TOGGLE_ON:
HwCfgRegister.Family_17h.CpbDis = !TurboBoost_Enable;
WRMSR(HwCfgRegister, MSR_K7_HWCR)With these ones
case COREFREQ_TOGGLE_OFF:
case COREFREQ_TOGGLE_ON:
HwCfgRegister.Family_17h.CpbDis = !TurboBoost_Enable;
HwCfgRegister.Family_17h.LockTscToCurrP0 = !HwCfgRegister.Family_17h.CpbDis;
WRMSR(HwCfgRegister, MSR_K7_HWCR)
Then check if the BCLK reading remains stable during OC and CPB
adatum
commented
5 years ago Which set of changes would you like me to test? I've already done git checkout HEAD corefreqk.c to erase previous code changes we tested.
What do you mean by "stable" for BCLK readings?
cyring
commented
5 years ago Just keep all code changes and please apply this last change which concerns LockTscToCurrP0
Then the purpose of the test is to do OC and CPB restoration.
What I try to do is to experiment the LockTscToCurrP0 bit and how it improves the BCLK
cyring
commented
5 years ago Sorry, apply this instruction:
HwCfgRegister.Family_17h.LockTscToCurrP0 = HwCfgRegister.Family_17h.CpbDis;(Fyi, it removes the not symbol)
adatum
commented
5 years ago BCLK shows ~99.81 MHz with the 37 ratio, but changing ratio also changes the BCLK reading. Reverting to 37 shows 99.81 MHz again.
OC 39, BCLK 94.69 MHz:
OC 38, BCLK 97.18 MHz :
Note that the MHz (eg. 3693) shown does not correspond to the ratio (eg. 38) nor to the max frequency under load (eg. 3793).
Restoring ratio to 37 restores the BCLK to 99.81 MHz:
The ratio and MHz correspond again as well.
Restoring CPB does not restore the boosted max frequencies; it's still capped at ~3700 MHz.
cyring
commented
5 years ago Thanks a lot. Probably that TSC-P0 bit has had a impact on OC. However the BCLK estimation makes things difficult to read, especially with the UI.
I suggest to pursue with argument AutoClock=0
I have to gather all code changes made so far, and to avoid confusion, I will use the factory base clock (yours: 100MHz) for static informations like the frequencies selector.
Edit: despite the factory base clock won't show any BCLK overclocking made in BIOS... and I'm back to square one.
adatum
commented
5 years ago I suggest to pursue with argument
AutoClock=0
To be clear, does 0 correspond to ON or OFF?
to avoid confusion, I will use the factory base clock (yours: 100MHz) for static informations like the frequencies selector.
Which would be fine unless the base clock is changed, which is possible (in BIOS).
cyring
commented
5 years ago | AutoClock | BCLK |
|---|---|
| 0 | Factory |
| 1 | Once |
| 2 | Dynamic |
cyring
commented
5 years ago Make use of P-States arguments to overclock when the driver is starting up (draft notes)
Family 0Fh: run the below function only when PState_FID or PState_VID are valued
https://github.com/cyring/CoreFreq/blob/f66676a8c45221a98088a35a560106714a9ef17c/corefreqk.c#L4098
Family 17h: overclock the max non boost frequency P0 when PState_FID is valued
https://github.com/cyring/CoreFreq/blob/f66676a8c45221a98088a35a560106714a9ef17c/corefreqk.c#L4486
if ( (PState_FID >= 0) && (PState_FID <= MAXCLOCK_TO_RATIO(Core->Clock.Hz)) )
{
CLOCK_ARG clockMod = {
.NC = CLOCK_MOD_MAX,
.Offset = PState_FID - Proc->Boost[BOOST(MAX)]
};
CLOCK_ZEN_ARG clockZen = { /* P0:Max non-boosted P-State */
.pClockMod = &clockMod,
.PstateAddr = MSR_AMD_PSTATE_DEF_BASE,
.BoostIndex = BOOST(MAX)
};
TurboBoost_Enable = COREFREQ_TOGGLE_OFF;
CC6_Enable = COREFREQ_TOGGLE_OFF;
PC6_Enable = COREFREQ_TOGGLE_OFF;
Query_AMD_Zen(Core);
TurboBoost_Enable = -1;
CC6_Enable = -1;
PC6_Enable = -1;
TurboClock_AMD_Zen_PerCore((void *) &clockZen);
}Closing the issue.
For next versions, I'm thinking about UI cells refreshment, such as the BCLK in Processor window; frequencies scale in OC; IMC estimation; and so on
To overclock the Zen family processors (from the UI):
To restore the Core Performance Boost:
Issue: the Base Clock estimation might get confused by these OC operations -> Disable "Auto Clock" in the [Settings] window