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d-iii-s / msim

Light-weight MIPS R4000 and RISC-V system simulator
https://d3s.mff.cuni.cz/software/msim/
GNU General Public License v2.0
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TLB simulation #36

Closed HanyzPAPU2 closed 1 year ago

HanyzPAPU2 commented 1 year ago

This pull request adds TLB simulation to RISC-V virtual translation scheme and implementis the SFENCE.VMA instruction.

Also a misunderstanding the WPRI CSRs has been fixed and a minor performance optimalization has been implemented.

HanyzPAPU commented 1 year ago

I reimplemented the TLB to be fully associative with a full LRU eviction strategy.

I also realized, that we can make the ASID recycle/steal tests fail if we make the TLB large enough for those tests. If there are more entries available than is the number of ASIDs, then this fully asociative cache will not have to evict any entries between the threads with the same ASID run (even if other 511 threads run in between).

I have tested this on DeutschOS and I have been able to fail these tests by not flushing the TLB correctly. The test ran with 520 threads and the full 512 available ASIDs.

vhotspur commented 1 year ago

I think we can merge this now. Thanks a lot!

But fefore doing that, would you, please, revert the version number changes you introduced? It works better for me if the versions are bumped directly in master rather than keeping the counter updated in various PRs. And I think I will do a major release anyway :-)