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d-iii-s / msim

Light-weight MIPS R4000 and RISC-V system simulator
https://d3s.mff.cuni.cz/software/msim/
GNU General Public License v2.0
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Add explain mode #58

Open vhotspur opened 8 months ago

vhotspur commented 8 months ago

Currently MSIM is able to print an alert when (CPU) exception is raised.

The idea behind this issue is to explain why the exception was raised. While it is often possible to determine the reason from various status registers, explicit explanation might help beginners understand the issue more quickly.

Below are to concrete examples where such information would was clearly missing and students were unable to quickly find out what were the actual reasons for the exception.

  1. When TLB refill is raised it might be worth stating that there is no such item or that there is such an item but with different ASID.
  2. Page fault (on RISC-V) should explain whether the reason is missing page table entry or missing SUM bit when supervisor tries to access user pages.
HanyzPAPU commented 8 months ago

When should this message be printed? Should we use trace mode for this, or would you prefer to introduce a new explain mode?

vhotspur commented 8 months ago

When should this message be printed?

Somewhere along the messages such as cpu%u raised TLB refill exception ....

Should we use trace mode for this, or would you prefer to introduce a new explain mode?

So far it is just an idea and I have not yet thought about out all the details. But I think it would be an extension of the trace mode, i.e. --explain would imply --trace.