The RISC-V privileged specification states: "Instruction address-translation and protection are unaffected by the setting of MPRV." on page 23.
MPRV is a bit in mstatus CSR which enables memory translation of memory loads and stores for M mode.
We currently translate all memory accesses when MPRV is set, which is incorrect behavior for instruction fetches, which should not be translated.
The RISC-V privileged specification states: "Instruction address-translation and protection are unaffected by the setting of MPRV." on page 23.
MPRV is a bit in mstatus CSR which enables memory translation of memory loads and stores for M mode. We currently translate all memory accesses when MPRV is set, which is incorrect behavior for instruction fetches, which should not be translated.