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d-m-bailey / cvc

CVC: Circuit Validity Checker. Check for errors in CDL netlist.
GNU General Public License v3.0
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SCRC real voltage values #135

Open d-m-bailey opened 6 years ago

d-m-bailey commented 6 years ago

Real simulation values for SCRC yield gate-source errors. for example, VDD 1.3V and VDDZ 1.1V. However, in SCRC mode, the VDDZ signals should all be low.

for SCRC power, do gate-source check after logic propagation, with logic low cancelling pmos errors and logic high cancelling nmos errors.

d-m-bailey commented 6 years ago

do not restrict to SCRC mode. Add option to have logic override worst case for gate checks.