d-m-bailey / cvc

CVC: Circuit Validity Checker. Check for errors in CDL netlist.
GNU General Public License v3.0
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Add ESD check for direct power connections to gates #259

Open d-m-bailey opened 5 months ago

d-m-bailey commented 5 months ago

Maybe allow a minimum resistance for power connections to gates.

The setting would be added to the model file where 0 ohm would be no check.

The check would only be for fixed gates (min=sim=max) to power.

Maybe flag any connection not equal to bulk/source net.

Power connections should be flagged for nmos and ground connections for pmos.