dalance / sv-parser

SystemVerilog parser library fully compliant with IEEE 1800-2017
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parameter array of strings causes an syntax error #101

Open fpgauserdude opened 1 month ago

fpgauserdude commented 1 month ago
localparam string TESTED_VERSIONS[] =
   {
     "2023.1",
     "2023.2"
    };

$ svinst test.sv files: parse failed: "test.sv" test.sv:72:42 | 72 | localparam string TESTED_VERSIONS[] = | ^

The syntax is maybe a little weird, but perfectly legal. This code compiles on a commercial tool.

dalance commented 1 month ago

According to Formal syntax of LRM, localparam can take unpacked_dimension only, so [] can't be used.

local_parameter_declaration ::= localparam data_type_or_implicit list_of_param_assignments
list_of_param_assignments ::= param_assignment { , param_assignment }
param_assignment ::= parameter_identifier { unpacked_dimension } [ = constant_param_expression ]
unpacked_dimension ::= [ constant_range ] | [ constant_expression ]
fpgauserdude commented 1 month ago

I changed the code to the following

localparam string TESTED_VERSIONS[2] =
   {
     "2023.1",
     "2023.2"
    };

And the parse does work.

But the only way I discovered this problem was by using sv-parse. Every other SystemVerilog tool that I am aware:.

Vivado, Questa, Quartus, even Verible (another FOSS tool) parse this code just fine.

dalance commented 1 month ago

For example, Synopsys Formality outputs syntax error to this code. A purpose of sv-parser is detecting such corner cases (almost all tools work fine, but some tools don't) by implementing as Formal syntax is.

fpgauserdude commented 1 month ago

I can appreciate the value of finding code that is not strictly compliant with the LRM. Sometimes I think that HDL tool vendors do not do the developer community any favors by allowing code that is non-compliant.