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dalance / sv-parser

SystemVerilog parser library fully compliant with IEEE 1800-2017
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Serialize an AST (question, not issue) #36

Open nblei opened 3 years ago

nblei commented 3 years ago

I need to modify gate level netlists by changing the input and output of individual gates. Currently, I'm doing this using PCRE. This is an inelegant and haphazard solution. I'd like to instead manipulate the AST generated by your parser, and then reserialize it. Is this currently supported? It does not seem to be.

If not, what do you think the best way to go about serializing the AST would be? My plan is to create tuple structs for each AST node struct which contains references to the the AST and to the node, and then implement the Display trait for these tuple structs.

I apologize if this was the wrong place to ask this question, but I did not see reference to mailing list, discord, etc.

erihsu commented 3 years ago

@nblei I think the basic goal of sv-parser is to help analyze SystemVerilog source code in the project. As it constructs full AST, basically you can get all information recorded in the source code. For easier use-case, you can define your self-use verilog parser(for low-level description) to get gate information and manipulate it then. I believe you'll get inspired from the repo https://github.com/eda-rs/netlist