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dalance / sv-parser

SystemVerilog parser library fully compliant with IEEE 1800-2017
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Parse error for multiple wildcard imports #54

Open huettern opened 2 years ago

huettern commented 2 years ago

When trying to parse the snitch IP I get a parse error, I guess due to the multiple import statements?

Error: parse error
   --> /tmp/snitch/hw/ip/snitch/src/snitch.sv:13:60
   |
13 | module snitch import snitch_pkg::*; import riscv_instr::*; #(
   |                                                            ^
Error: Parse error: Some(("/tmp/snitch/hw/ip/snitch/src/snitch.sv", 490))

Steps to reproduce

git clone --depth=1 git@github.com:pulp-platform/snitch.git
cd snitch/hw/ip/snitch
bender sources -f > sources.tcl
morty -f sources.tcl
huettern commented 2 years ago

CC: @zarubaf

DaveMcEwan commented 2 years ago

I think sv-parser does the correct thing here. The correct syntax is module snitch import snitch_pkg::*, riscv_instr::*; #(.

In the LRM (IEEE1800-2017), page 697 shows an except from Annex A, where module_ansi_header permits a single optional package_import_declaration. The definition of package_import_declaration shown on page 777 allows multiple comma-separated package_import_item.

zarubaf commented 2 years ago

@DaveMcEwan Indeed I agree after looking into the Language Manual. Interesting, that most of the tools have no problem with the ; though.

p. 781 also gives an example:

module M import A::instruction_t, B::*; #(WIDTH = 32)
...
(input [WIDTH-1:0] data, input instruction_t a, output [WIDTH-1:0] result, output boolean_t OK
); endmodule: M